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參數(shù)資料
| 型號： | PDC2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 291K |
| 代理商： | PDC2 |
6
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
Scan Test
Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan out-
puts can be observed. In order to achieve this, the ATPG vectors must be generated on the
entire circuit (top-level) which includes the PDC2, or all PDC2 I/Os must have a top level
access and ATPG vectors must be applied to these pins.
Configuration
The PDC2 has a standard Atmel Bridge interface that enables the user to configure and con-
trol the data transfers for each channel. The user interface of a PDC2 channel is integrated
into the user interface of the peripheral which it is related to. Per peripheral, it contains four 32-
bit Pointer Registers (RPR, RNPR, TPR, TNPR) and four 16-bit Counter Registers (RCR,
RNCR, TCR, TNCR).
The size of the transfer (number of transfers) is configured in an internal 16-bit transfer
counter register, and it is possible, at any moment, to read the number of transfers left for each
channel.
The base memory address is configured in a 32-bit memory pointer, by defining the location of
the first access point in the memory. It is possible, at any moment, to read the location in mem-
ory of the next transfer.
The PDC2 has dedicated status registers which indicate if transfer is enabled or disabled for
each channel
—
the remaining status for each channel is located in the peripheral. Transfers
can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC2
Transfer Control Registers. The PDC2 sends status flags (periph_rx_end, periph_tx_end,
rx_buffer_full, tx_buffer_empty) to the peripheral, which can latch the flags in its status
register.
System Bus
Interface
The PDC2 interfaces with the AMBA System Bus (ASB) and generates all the control signals
for interfacing with a Memory Management Unit or EBI for memory read and write.
Memory
Pointers
Each peripheral is connected to the PDC2 by a receive data channel and a transmit data
channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to
a location in the system bus memory space (on-chip memory or external bus interface
memory).
Depending on the type of transfer (byte, half-word or word), the memory pointer is incre-
mented by 1, 2 or 4, respectively for peripheral transfers.
memory_write
Memory Write from Peripheral
Output
High
Used by Memory Management Unit or EBI to
select data coming from masters or
peripherals (Bridge)
Test Scan
scan_test_mode
Clock Selection for Test
Purposes
Input
High
Tied to 1 during scan test
–
tied to 0 when in
function mode
test_se
Scan Test Enable
Input
High
/Low
Scan shift/scan capture
test_si [(1+per_n):1]
Scan Test Input
Input
–
Entry of scan chain
test_so [(1+per_n):1]
Scan Test Output
Output
–
Ouput of scan chain
Table 1.
PDC2 Pin Description (Continued)
Name
Definition
Type
Active
Level
Comments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1284P11 | 3.3V Parallel interface transceiver/buffer |
| PDI1394P11A | 3-port physical layer interface |
| PDI1394P11ABD | 3-port physical layer interface |
| PDI1394P25BY | 1-port 400 Mbps physical layer interface |
| PDI20AC1H0R | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDC-20-1 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
| PDC-20-1W | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
| PDC20275 | 制造商:PROMISE 功能描述: 制造商:Promise Tech 功能描述: |
| PDC20275-E3 | 制造商:Promise Tech 功能描述: |
| PDC-20-3 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
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