11
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
Figure 5.
APB to ASB Transfer with Zero Wait States Memory Followed by an APB Access Made by Another Master
clock
areq (PDC2)
agnt (PDC2)
bridge_sel
agnt (other master)
bwait
bwrite
ba[31:0]
PDC2 status
bwrite (ASB)
ba[31:0] (ASB)
memory_write
pdc_size[1:0]
pdc_write
pdc_add[20:0]
pdc_sel
brdata[31:0]
periph_stb
pstb_rising
periph_add[13:0]
periph_write
data_to_master[31:0]
(output of the bridge)
done
done
wait
Memory Address
Transfer
NOT GRANTED
NOT GRANTED
Peripheral Address
Data from Bridge
14'h0000
Peripheral Address
Address from Master
14'h0000
bwrite from Master
Previous Data
Data for PDC Transfer
Data for Master
done
done
Locked Idle Cycle
bwrite from Master
Memory Address
ba from Master
Data from Memories
14'h0000