參數(shù)資料
型號: PCF8811
廠商: NXP Semiconductors N.V.
英文描述: 80 x 128 pixels matrix LCD driver
中文描述: 80 × 128像素矩陣LCD驅(qū)動器
文件頁數(shù): 50/73頁
文件大小: 434K
代理商: PCF8811
2004 May 17
50
Philips Semiconductors
Product specification
80
×
128 pixels matrix LCD driver
PCF8811
20 I
2
C-BUS INTERFACE TIMING CHARACTERISTICS
V
DD1
= 1.8 V to 3.3 V; V
SS
= 0 V; V
LCD
= maximum 9.0 V; T
amb
=
40
°
C to +85
°
C; note 1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fs-mode;
see Fig.41
f
SCLH
t
SU;STA
SCLH clock frequency
set-up time (repeated) START
condition
hold time (repeated) START
condition
LOW period of the SCLH clock
HIGH period of the SCLH clock
data set-up time
data hold time
SCL and SDA rise time
SCL and SDA fall time
capacitive load represented by
each bus line
set-up time for STOP condition
tolerable spike width on bus
bus free time between START
and STOP condition
noise margin at the LOW level
for each connected device
(including hysteresis)
noise margin at the HIGH-level
for each connected device
(including hysteresis)
0
600
400
kHz
ns
t
HD;STA
600
ns
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
b
1300
600
100
0
20 + 0.1C
b
20 + 0.1C
b
900
300
300
400
ns
ns
ns
ns
ns
ns
pF
note 2
note 2
t
SU;STO
t
SP
t
BUF
600
1300
50
ns
ns
ns
V
nL
0.1V
DD1
V
V
nH
0.2V
DD1
V
Hs-mode;
see Fig.42
f
SCLH
t
SU;STA
SCLH clock frequency
set-up time (repeated) START
condition
hold time (repeated) START
condition
LOW period of the SCLH clock
HIGH period of the SCLH clock
data set-up time
data hold time
rise time of the SCLH signal
rise time of the SCLH signal
after the acknowledge bit
fall time of the SCLH signal
rise time of the SDAH signal
fall time of the SCLH signal
0
160
3.4
MHz
ns
t
HD;STA
160
ns
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
rCL
t
rCL1
160
60
10
20
10
10
70
40
80
ns
ns
ns
ns
ns
ns
t
fCL
t
rDA
t
fCL1
10
10
10
40
80
80
ns
ns
ns
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