1998 Nov 02
86
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
Notes
1.
DC/DC converter configured with inductor of L = 470
μ
H, SRL = 5
, input capacitance of C
i
= 4.7
μ
F, ESR = 0.5
,
V
DD
output capacitor C
o
= 4.7
μ
F, ESR = 0.5
, R
BAT
< 1
.
This parameter is not tested during production; it is guaranteed by design.
This parameter depends on external components.
At high load or low battery voltage the inductor charge time can be extended to a full XTL1 period, while the minimum
inductor discharge time is a half XTL1 period.
The execution time is strongly dependant on command type and addressing mode (see also Table 60).
2.
3.
4.
5.
ZIF (I and Q) demodulator
f
offset
t
(ENA-AVG)
t
ENB
offset from 0 frequency
ENA to valid AVG value
ENB to valid
demodulator output
ENB to correct recovered
clock
note 2
3 kHz offset; note 2
note 2
6
100
1
kHz
ms
symbol
duration
t
ENC
note 2
phase error curves apply (see Fig.27)
All outputs
t
r,f
rise and fall times for
outputs
C
L
= 20 pF
15
ns
Open-drain pins SDA and SCL (P1.7 and P1.6)
t
n
V/
t
noise suppression filter
slope for the falling edge
60
50
ns
ns/V
R
L
= 20 k
; C
L
= 50 pF;
V
DD
= 2.2 V
R
L
= 20 k
; C
L
= 50 pF
V
DD
= 2.2 V; R
L
= 20 k
;
C
L
= 50 pF
dI/dt
I
o(sink)(swL)
slope for both edges
dynamic output sink
current during switching
low (Miller compensated)
250
2
μ
A/ns
mA
OTP programming characteristics
V
SU;PP
t
W(prog)
t
W(prog)(sec)
V
PP
set-up time
program pulse width
program pulse security
bits
program pulse recover
time
10
100
200
μ
s
μ
s
μ
s
t
W(prog)(rec)
1
μ
s
AFC-DAC
t
start(DAC)
start-up time disabled
DAC to stable output for
code 111111
power supply ripple
rejection (V
DD
-> DAC)
slew time for analog
output from 10 to 90%
for a voltage step of 1 V
note 2
50
100
μ
s
PSRR
0
dB
t
slew
code 010000 <-> 110000
2.5
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT