參數(shù)資料
型號： PCA5010
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機基帶控制器
文件頁數(shù)： 43/112頁
文件大小： 627K
代理商： PCA5010
1998 Nov 02
43
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
SFR:
TFREQ0 to TFREQ7: 8-bit register containing the
divisor of the tone. Loaded by the processor.
ENB: enable frequency generator. Control signal from
processor.
CLK2: use secondary clock input for tone generation.
If set a 32768 Hz clock signal is generated from the
primary 76800 Hz clock signal and used as a timing
reference for the tone generator.
Inputs:
76.8 kHz: Input to the tone counter.
Outputs:
AT Output for alerter. Is logic 0 when disabled:
TFREQ
6.15.3
G
ENERATION OF THE
32768 H
Z REFERENCE
The 32768 Hz reference is generated from 76800 Hz
according to the following algorithm:
forever do
begin
for 10 times do {
from 7 clocks on 76.8 kHz generate
3 pulses on 32 kHz
}
from 5 clocks on 76.8 kHz generate
2 pulses on 32 kHz
end
f
AT
76.8 kHz
=
6.16
Watchdog timer
6.16.1
F
UNCTION
The watchdog timer consists of an 8-bit down counter.
The binary number defined with WD3 to WD0 defines the
expiration time of the watchdog timer between 1 to 16 s.
Once enabled this counter is running continuously. Once
expired the timer produces firstly an interrupt and finally a
reset. The software must reload the watchdog in regular
intervals to avoid expiration.
A positive edge on the LD SFR bit (re)loads the counter
with the value of WD3 to WD0, sets the LOW bits to logic 1
and activates this counter if it is not yet running. However,
to prepare the (re)loading a positive edge must be applied
to the COND bit in WDCON. In this way at least two
locations in software must be passed before the counter
can be reloaded.
After reset the counter is not running. Only after the first LD
it is clocked continuously by a clock pulse of 16 Hz until the
DC/DC converter is switched off or an external reset is
applied.
If the next LD signal is not given within the defined expiry
interval an overflow occurs and the processor will be reset
(signal WDR). 1 clock cycle before the reset is applied an
WDI interrupt is issued. This gives the opportunity to avoid
the reset if required. The maximum watchdog expiry time
is thus 254
×
16 Hz ticks to the WD interrupt and
255
×
16 Hz ticks to the reset. If the DC/DC converter is in
the off mode, the watchdog timer is suspended.
6.16.2
W
ATCH
D
OG
T
IMER
C
ONTROL
R
EGISTER
(WDCON)
The WDCON special function register is used to control the operation of the on-chip watchdog timer.
Table 34
Watchdog Control Register (WDCON, SFR address A5H)
Table 35
Description of the WDCON bits
7
6
5
4
3
2
1
0
COND
WD3
WD2
WD1
WD0
LD
BIT
SYMBOL
FUNCTION
WDCON.7
WDCON.6
WDCON.5
WDCON.4
WDCON.3
COND
WD3
WD2
WD1
WD0
Load condition
. Control signal from processor.
WD0 to WD3 is the preset value for the high nibble of the watchdog timer. The value is
the number of seconds to expiry of the watchdog.
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