參數資料
型號: PCA5010
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數: 31/112頁
文件大?。?/td> 627K
代理商: PCA5010
1998 Nov 02
31
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.11
Clock correction
6.11.1
F
UNCTION
The clock correction block is connected to the 76.8 kHz
oscillator. It operates directly on V
BAT
. By means of the
clock correction circuit a digital adjustment of the 76.8 kHz
oscillator signal is implemented.
An 18-bit interval counter inserts or deletes one pulse from
the 76.8 kHz clock each time its count has expired.
The interval is stored by the processor to the 18-bit interval
register CIV. Addition/deletion is performed by hardware.
Crystal offset correction can be performed with a
resolution of 5 ppm.
This block also generates the timing reference signals for
other functional blocks such as the RTC (4 Hz), watchdog
(16 Hz), Timer 0 (256 Hz), wake-up counter (9600 Hz)
and the demodulator/clock recovery block. The generation
of these timing references is always active and cannot be
disabled.
Fig.15 Block diagram of clock compensation.
handbook, full pagewidth
MGR116
Q
D
Q
R
D
1
STORE
76.8 kHz
corrected
38.4 kHz
internal
set flag
SFR to
microcontroller
RESET
with each
OFF cycle
SET
ENB
PLUS
BYPASS
TEST
CIV0 to CIV17
INTERVAL LATCH
(18-BIT)
reload data
INTERVAL COUNTER
(18-BIT)
(RELOAD ON CARRY)
&
VDD supply
RESET only
on RESETIN
CARRY
ADD/DELETE
ONE PULSE
ON CARRY
÷
2
VBAT supply
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