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參數(shù)資料
| 型號： | PCA5010 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機(jī)基帶控制器 |
| 文件頁數(shù)： | 12/112頁 |
| 文件大小： | 627K |
| 代理商： | PCA5010 |
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1998 Nov 02
12
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.5
Addressing
The PCA5010 has five methods for addressing source
operands:
Register
Direct
Register-Indirect
Immediate
Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
Access to memory addressing is as follows:
Registers in one of the four 8-register banks through
Register Direct or Register-Indirect
Maximum 1280 bytes of internal data RAM through
Direct or Register-Indirect
– Bytes 0 to 127 of internal RAM may be addressed
directly/indirectly. Bytes 128 to 255 of internal RAM
share their address location with the SFRs and so
may only be addressed Register-Indirect as data
RAM.
– Bytes 0 to 1024 of AUX-RAM can be addressed
indirectly via MOVX. Bytes 256 to 1024 can only be
addressed using indirect addressing with the data
pointer, while bytes 0 to 255 may be also addressed
using R0 or R1.
Special function registers through Direct
Program memory Look-Up Tables (LUTs) through
Base-Register plus Index-Register-Indirect.
The PCA5010 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers (SFRs),
Arithmetic Logic Unit (ALU) and external data bus are all
8-bits wide. It performs operations on bit, nibble, byte and
double-byte data types.
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
While the PCA5010 is executing code from the internal
memory, ALE and PSEN pins are inactive with
ALE = LOW and PSEN = HIGH.
External XRAM is not supported for this device, since P3.7
(RD) and P3.6 (WR) pins are not available. If the external
XRAM is accessed accidentally, no PSEN or ALE cycle is
done and actual P0 values are read. Internal XRAM
access is not visible from outside the chip (no ALE, PSEN,
P0 and P2 activity).
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相關(guān)代理商/技術(shù)參數(shù) |
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| PCA5010H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
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