1998 Nov 02
56
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.19.4
P
ORT
3
INTERRUPTS
: P3.2
AND
P3.3
INT0 and INT1 are level or edge sensitive.
The programming is performed with TCON. Since P3.2
and P3.3 are configured as push-pull outputs, these
interrupts can only be triggered by output commands to
these ports and not by external events.
TCON.0 (IT0):
Interrupt 0 type control bit. Set/cleared by
software to specify falling edge/low level triggered
external interrupt (see Fig.30).
TCON.1 (IE0):
Interrupt 0 flag. Set by hardware when
an external interrupt is detected. Cleared by hardware
when the service routine is called.
TCON.2 (IT1):
Interrupt 1 type control bit. Set/cleared by
software to specify falling edge/low level triggered
external interrupt.
TCON.3 (IE1):
Interrupt 0 flag. Set by hardware when
an external interrupt is detected. Cleared by hardware
when the service routine is called.
6.19.5
W
AKE
-
UP INTERRUPT
The wake-up interrupt (T2) is the level sensitive
OR-function of WUP bit or CPL bit in the WUCON SFR.
The wake-up interrupt is mapped to the T2 vector
(see Fig.30). These flags are set by hardware and need to
be cleared by software. For more information see
Section 6.14.
WUCON.6 (WUP):
WUP interrupt flag. Attention: writing
and reading this SFR bit does not access the same flag.
The flag is set by hardware and needs to be cleared by
software.
WUCON.4 (CPL):
Complete flag. The previous set
instruction is completed. The settings of the SFR have
been copied to the peripheral block. The flag is set by
hardware and needs to be cleared by software.
Fig.30 External interrupt Port 3.2 and Port 3.3 (INT0 and INT1).
handbook, full pagewidth
Pad Port 3.2
MGR126
IT0
INT0
X0
IE0
(interrupt edge flag)
0
1
Fig.31 Wake-up interrupt.
handbook, full pagewidth
MGR1127
WAKE-UP
COUNTER
WUP
CPL
T2
≥
1