參數(shù)資料
型號: PCA5010
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機(jī)基帶控制器
文件頁數(shù): 55/112頁
文件大小: 627K
代理商: PCA5010
1998 Nov 02
55
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
Notes
1.
IEN0 and IEN1: These are two 8-bit registers that control the enabling of the 15 interrupt sources individually as well
as a global enable/disable for all of the sources.
IP0 and IP1: These are two 8-bit registers that set priority for each interrupt source. IP0 actually contains only 7 bits
as IP.7 is not implemented. This bit will always read as logic 0.
2.
3
IQ5
SYMBOL
Interrupt request flag from clock recovery circuit. Set by hardware or software. Cleared
by software.
Interrupt request flag from P1.4.
Interrupt request flag from DC/DC-CONVERTER. Set by hardware or software. Cleared
by software.
Interrupt request flag from watchdog timer. Set by hardware or software. Cleared by
software.
Interrupt request flag from real-time clock interrupt. Set by hardware or software.
Cleared by software.
4
5
IQ6
IQ7
P1.4
DC/DC
6
IQ8
WDI
7
IQ9
MIN
WUCON address 94H: wake-up counter control register
Latch signal to copy content of WUC to peripheral register.
1
LOAD
Parallel load signal for wake-up counter.
2
Z0
3
Z1
4
CPL
Complete interrupt flag from wake-up counter timer. Set by hardware or software.
Cleared by software.
5
unused
6
WUP
WUP interrupt flag from wake-up counter timer. Set by hardware or software. Cleared by
software.
7
RUN
RUN bit for wake-up counter.
0
SET
RTCON address CDH: real-time clock control register
1
LOAD
2
W/R
3 to 6 unused
7
MIN
0
SET
Latch signal to copy content of WUC to peripheral register.
Load RTC0 value from SFR to RTC.
Disable write back to SFR.
Interrupt request flag from RTC. Set by hardware or software. Cleared by software.
BITS
CONV.
NAME
SOURCE
NOTES
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