參數(shù)資料
型號： PC8260VTPU200
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁數(shù)： 30/53頁
文件大?。?/td> 364K
代理商： PC8260VTPU200
30
PC8260PowerQUICCII
2131B–HIREL–02/03
L_A29
PCI_INTA
LocalBusAddress29
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIINTA
I/O
WhenthePowerQUICCIIisthehostinthePCIsystem,thispinisan
inputfordeliveringPCIinterruptstothehost.WhenthePowerQUICCII
isnotthehostofthePCIsystem,thispinisanoutputusedbythe
PowerQUICCIItosignalaninterrupttothePCIhost.
L_A30
LocalBusAddress30
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
L_A31
DLLSYNC
LocalBusAddress31
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
DLLSynchronization
I
DLLSYNCisusedtoeliminateskewfortheclockdrivenonCLKOUT.
LCL_D[0:31]
PCI_AD[0:31]
LocalBusData
I/O
Inthelocaldatabus,bit0ismostsignificantandbit31isleast
significant.
PCIAddressData
I/O
PCIbusaddressdatainput/outputpins.InthePCIaddressdatabus,bit
31ismostsignificantandbit0isleastsignificant.
LCL_DP[0:3]
PCI_C/BE[0:3]
LocalBusDataParity
I/O
InlocalbuswriteoperationsthePowerQUICCIIdrivesthesepins.In
localbusreadoperationstheaccesseddevicedrivesthesepins.
LCL_DP(0)isdrivenwithavaluethatgivesoddparitywithLCL_D(0:7).
LCL-DP(1)isdrivenwithavaluethatgivesoddparitywithLCL_D(8:15).
LCL_DP(2)isdrivenwithavaluethatgivesoddparitywith
LCL_D(16:23).
LCL_DP(3)isdrivenwithavaluethatgivesoddparitywith
LCL_D(24:31)
PCPCommand/Byte
Enable
I/O
ThePowerQUICCIIdrivesthesepinswhenitistheinitiatorofaPCI
transfer.
IRQ0
NMI_OUT
Interruptrequest0
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theNMI-OUTinternalinterruptcontroller)aserviceroutinefromthe
core.
NonMaskableInterrupt
Output
O
ThisisanoutputdrivenfromPowerQUICCII’sinternalinterrupt
controller.Assertionofthisoutputindicatesthatanunmaskedinterrupt
ispendinginPowerQUICCII’sinternalinterruptcontroller.
IRQ7
INT_OUT
APE
InterruptRequest7
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
InterruptOutput
O
ThisisanoutputdrivenfromPowerQUICCII’sinternalinterrupt
controller.Assertionofthisoutputindicatesthatanunmaskedinterrupt
ispendinginPowerQUICCII’sinternalinterruptcontroller.
AddressParityError
O
ThisoutputpinwillbeassertedwhenthePowerQUICCII’sdetects
wrongparitydrivenonitsaddressparitypinsbyanexternalmaster
TRST
TestReset(JTAG)
I
ThisistheresetinputtoPowerQUICCII’sJTAG/COPcontroller.
TCK
TestClock(JTAG)
I
ThispinprovidestheclockinputforPowerQUICCII’sJTAG/COP
controller.
TMS
TestModeSelect(JTAG)
I
ThispincontrolsthestateofPowerQUICCII’sJTAG/COPcontroller.
TDI
TestDataIn(JTAG)
I
ThispinisthedatainputtoPowerQUICCII’sJTAG/COPcontroller.
TDO
TestDataOut(JTAG)
O
ThispinisthedataoutputfromPowerQUICCII’sJTAG/COPcontroller.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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