參數(shù)資料
型號(hào)： PC8260VTPU200
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁(yè)數(shù)： 26/53頁(yè)
文件大?。?/td> 364K
代理商： PC8260VTPU200
26
PC8260PowerQUICCII
2131B–HIREL–02/03
PWE[0:7]
PSDDQM[0:7]
PBS[0:7]
60xBusWriteEnable
O
Outputsofthe60xbusGPCM,thesepinsselectbytelanesfor
PSDDQM[0-7]writeoperations.
60xBusSDRAMDQM
O
TheDQMpinsareoutputsoftheSDRAMcontrolmachine.Thesepins
selectspecificbytelanesofSRAMdevices.
60xBusUPMByteSelect
O
ThebyteselectpinsareoutputsoftheUPMinthememorycontroller.
Theyareusedtoselectspecificbytelanesduringmemoryoperations.
ThetimingofthesepinsisprogrammedintheUPM.Theactualdriven
valuedependsontheaddressandsizeofthetransactionandtheport
sizeoftheaccesseddevice.
PSDA10
PGPLO
60xBusSDRAMA10
O
Anoutputfromthe60xbusSDRAMcontroller,thispinispartofthe
addresswhenarowaddressisdrivenandispartofthecommandwhen
acolumnaddressisdriven.
60xBusUPMGeneral
PurposeLine0
O
ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues
andtimingofthispinareprogrammedintheUPM;
PSDWE
PGPL1
60xBusSDRAMWrite
Enable
O
Anoutputfromthe60xbusSDRAMcontroller.Thispinshouldbe
connectedtoSRAM’sWEinput.
60xBusUPMGeneral
PurposeLine1
O
ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues
andtimingofthispinareprogrammedintheUPM.
POE
PSDRAS
PGPL2
60xBusOutputEnable
O
Theoutputenablepinisanoutputofthe60xbusGPCM.Thispin
controlstheoutputbufferofmemorydevicesduringreadoperations.
60xBusSDRAMRAS
O
Outputfromthe60xbusSDRAMcontroller.Thispinshouldbe
connectedtoSDRAM’sRASinput.
60xBusUPMGeneral
PurposeLine2.
O
ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues
andtimingofthispinareprogrammedintheUPM.
PSDCAS
PGPL3
60xbusSDRAMCAS
O
Outputfromthe60xbusSDRAMcontroller.Thispinshouldbe
connectedto
SDRAM’sCAS
input.
60xBusUPMGeneral
Purposeline3
O
ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues
andtimingofthispinareprogrammedintheUPM.
PGTA
PUPMWAIT
PGPL4
PPBS
60xGPCMTA
I
ThisinputpinisusedfortransactionterminationduringGPCM
operation.Thispinrequiresexternalpullupresistorforproperoperation.
60xBusUPMWait
I
ThisisaninputtotheUPM.Anexternaldevicemayholdthispinlowto
forcetheUPMtowaituntilthedeviceisreadyforthecontinuationofthe
operation.
60xBusUPMGeneral
PurposeLine4
O
ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues
andtimingofthispinareprogrammedintheUPM.
60xBusParityByteSelect
O
Insystemsinwhichdataparityisstoredinaseparatechip,thisoutputis
usedasthebyteselectforthatchip.
PSDAMUX
PGPL5
60xSDRAMAddress
Multiplexer
O
Thisoutputpincontrolsthe60xSDRAMaddressmultiplexerwhenthe
PowerQUICCIIisinexternalmastermode.
60xBusGeneralPurpose
Line5
O
ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues
andtimingofthispinareprogrammedintheUPM.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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