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參數(shù)資料
| 型號： | PC8260VTPU200 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC-based Communications Processors |
| 中文描述： | 基于PowerPC的通信處理器 |
| 文件頁數(shù)： | 28/53頁 |
| 文件大小： | 364K |
| 代理商： | PC8260VTPU200 |
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PC8260PowerQUICCII
2131B–HIREL–02/03
L_A14
PCI_PAR
LocalBusAddress14
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIParity
I/O
Assertionofthispinindicatesthatoddparityisdrivenacross
PCI_AD[0:31]andPCI_C/BE[0-3]duringaddressanddataphases.
Negationofthispinindicatesthatevenparityisdrivenacrossthe
PCI_AD[0-31]andPCI_C/BE[0-3]signalsduringaddressanddata
phases.
L_A15
PCI_FRAME
SMI
LocalBusAddress15
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIFramei
I/O
ThispinisdrivenbythePowerQUICCIIwhenitsinterfaceistheinitiator
ofaPCItransfer.ThispinisassertedtoindicatethataPCItransferison
going.
SystemManagement
Interrupt
I
Systemmanagementinterruptinputtothecore.
L-A16
PCI_TRDY
LocalBusAddress16
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCITargetReady
I/O
ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe
targetofaPCItransfer.AssertionofthispinindicatesthatthePCItarget
isreadytosendoracceptadatabeat.
L_A17
PCI_IRDY
CKSTP_OUT
LocalBusAddress17
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIInitiatorReady
I/O
ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe
initiatorofaPC]transfer.AssertionofthispinindicatesthatthePCI
initiatorisreadytosendoracceptadatabeat.
CheckstopOutput
O
AssertionofCKSTP_OUTindicatesthecoreisincheckstopmode.
L_A18
PCI_STOP
LocalBusAddress18
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIStop
I/O
ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe
targetofaPCItransfer.AssertionofthispinindicatesthatthePCItarget
isrequestingtostopthePCItransfer.
L_A19
PCI_DEVESEL
LocalBusAddress19
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIDeviceSelect
I/O
ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe
targetofaPCItransfer.AssertionofthispinindicatesthataPCItarget
hasrecognizedanewPCItransferwithanaddressthatbelongstothe
PCItarget.
L_A20
PCI_IDSEL
LocalBusAddress20
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIIDselect
I
UsedtoselectPowerQUICCII’sPCIinterfaceduringaPCIconfiguration
cycle.
L_A21
PCI_PERR
LocalBusAddress21
O
Inthelocaladdressbus,bit14ismostsignificantandbit31isleast
significant.
PCIParityError
I/O
Assertionofthispinindicatesthataparityerrorwasdetectedduringa
PCItransfer.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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