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參數(shù)資料
| 型號： | PC8260VTPU200 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC-based Communications Processors |
| 中文描述： | 基于PowerPC的通信處理器 |
| 文件頁數(shù)： | 24/53頁 |
| 文件大?。?/td> | 364K |
| 代理商： | PC8260VTPU200 |
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PC8260PowerQUICCII
2131B–HIREL–02/03
PSDVAL
60xDataValid
I/O
AssertionofthePSDVALpinindicatesthatadatabeatisvalidonthe
databus.ThedifferencebetweentheTApinandthePSDVALpinisthat
theTApinisassertedtoindicate60xdatatransferterminations,while
thePSDVALsignalisassertedwitheachdatabeatmovement.Thus,
alwayswhenTAisasserted,PSDVALwillbeasserted,but,when
PSDVALisasserted,TAisnotnecessarilyasserted.Forexample,when
adouble-doubleword(2x64bits)transferisinitiatedbytheSDMAtoa
memorydevicethathas32bitsportsize,PSDVALwillbeasserted3
timeswithoutTAand,finally,bothpinswillbeassertedtoterminatethe
transfer.
TA
TransferAcknowledge
I/O
AssertionoftheTApinindicatesthata60xdatabeatisvalidonthedata
bus.For60xsinglebeattransfers,assertionofthispinindicatesthe
terminationofthetransfer.For60xbursttransfers,thispinwillbe
assertedfourtimestoindicatethetransferoffourdatabeats,withthe
lastassertionindicatingtheterminationofthebursttransfer.
TEA
TransferError
Acknowledge
I/O
Assertionofthispinindicatesabuserror.60xmasterswithinthe
PowerQUICCIImonitorthestateofthispin.PowerQUICCII’sinternal
busmonitormayassertthispinifithasidentifieda60xtransferthatis
hung.
GBL
IRQ1
Global
I/O
Whena60xmasterwithinthechipinitiatesabustransactionitdrives
thispin.Whenanexternal60xmasterinitiatesabustransaction,it
shoulddrivethispin.Assertionofthispinindicatesthatthetransferis
globalanditshouldbesnoopedbycachesinthesystem.The
PowerQUICCIIdatacachemonitorsthestateofthispin.
InterruptRequest1
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
CI
BADDR29
IRQ2
CacheInhibit
O
Thispinisanoutputpin.ItisusedforL2cachecontrol.Foreach
BADDR29PowerQUICCII60xtransactioninitiatedinthecore,thestate
ofthispinindicatesifthistransactionshouldbecachedornot.Assertion
oftheCIpinindicatesthatthetransactionshouldnotbecached.
BurstAddress29
O
Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe
60xmemorycontroller.Thesepinsareusedinexternalmaster
configurationandareconnecteddirectlytomemorydevicescontrolled
byPowerQUICCIImemorycontroller.
InterruptRequest2
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
WT
BADDR30
IRQ3
WriteThrough
O
OutputusedforL2cachecontrol.ForeachcoreinitiatedPowerQUICCII
60xtransaction,thestateofthispinindicatesifthetransactionshouldbe
cachedusingwrite-throughorcopy-backmode.AssertionofWT
indicatesthatthetransactionshouldbecachedusingthewrite-through
mode.
BurstAddress30
O
Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe
60xmemorycontroller.Thesepinsareusedinexternalmaster
configurationandareconnecteddirectlytomemorydevicescontrolled
byPowerQUICCII’smemorycontroller.
InterruptRequest3
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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