參數(shù)資料
型號： PC8260VTPU200
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁數(shù)： 22/53頁
文件大小： 364K
代理商： PC8260VTPU200
22
PC8260PowerQUICCII
2131B–HIREL–02/03
DBG
60xDataBusGrant
I/O
Thisisanoutputwhenaninternalarbiterisusedandaninputwhenan
externalarbiterisused.Asanoutput,thePowerQUICCIIassertsthis
pintogrant60xdatabusownershiptoanexternalbusmaster.Asan
input,theexternalarbitershouldassertthispintogrant60xdatabus
ownershiptothePowerQUICCII.
DBB
IRQ3
60xDataBusBusy
I/O
AsanoutputthePowerQUICCIIassertsthispinforthedurationofthe
databustenure.FollowingaTA,whichterminatesthedatabustenure,
thePowerQUICCIInegatesDBBforafractionofabuscycleandthen
stopsdrivingthispin.Asaninput,thePowerQUICCIIwillnotassume
60xdatabusownership,aslongasitsensesthispinisassertedbyan
external60xbusmaster.
InterruptRequest3
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
D[0:63]
60xDataBus
I/O
Inwritetransactions,the60xbusmasterdrivesthevaliddataonthis
bus.Inreadtransactions,the60xslavedrivesthevaliddataonthisbus.
DP[0]
RSRV
EXTBR2
60xDataParity0
I/O
The60xagentthatdrivesthedatabus,alsodrivesthedataparity
signals.Thevaluedrivenonthedataparity0pinshouldprovideodd
parity(oddnumberof1’s)onthegroupofsignalsthatincludedataparity
0andD[0:7].
Reservation
O
Thevaluedrivenonthisoutputpinrepresentsthestateofthecoherency
bitinthereservationaddressregisterthatisusedbythe
Iwarx
and
stwcx.instructions.
ExternalBusRequest2
I
Anexternalmastershouldassertthispintorequest60xbusownership
fromtheinternalarbiter.
IRQ1
DP[1]
EXTBG2
InterruptRequest1
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
60xDataParity1
I/O
The60xagentthatdrivesthedatabus,alsodrivesthedataparity
signals.Thevaluedrivenonthedataparity1pinshouldprovideodd
parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata
parity1andD[8:15].
ExternalBusGrant2
O
ThePowerQUICCIIassertsthispintogrant60xbusownershiptoan
externalbusmaster.
IRQ2
DP[2]
TLBISYNC
EXTDBG2
InterruptRequest2
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
60xDataParity2
I/O
The60xagentthatdrivesthedatabus,alsodrivesthedataparity
signals.Thevaluedrivenonthedataparity2pinshouldprovideodd
parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata
parity2andS[16:23].
TLBSync:
I
Thisinputpincanbeusedtosynchronize60xcoreinstructionexecution
tohardwareindications.Assertingthispinwillforcethecoretostop
instructionexecutionfollowingatlbsinc
instructionexecution.Thecore
resumesinstructionexecutiononcethispinisnegated.
ExternalDataBusGrant2
O
ThePowerQUICCIIassertsthispintogrant60xdatabusownershipto
anexternalbusmaster.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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