參數(shù)資料
型號(hào)： PC8260VTPU200
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁(yè)數(shù)： 21/53頁(yè)
文件大?。?/td> 364K
代理商： PC8260VTPU200
21
PC8260PowerQUICCII
2131B–HIREL–02/03
SignalDescriptions
ThePowerQUICCIIsystembussignalsconsistofallthelinesthatinterfacewiththeexternalbus.Manyoftheselinesper-
formdifferentfunctions,dependingonhowtheuserassignsthem.Eachsignal’spinnumbercanbefoundinTable4.
Table4.
ExternalSignals
Pin
SignalName
Type
Description
BR
60xBusRequest
I/O
Thisisanoutputwhenanexternalarbiterisusedandaninputwhenan
internalarbiterisused.Asanoutput,thePowerQUICCIIassertsthispin
torequestownershipofthe60xbus.Asaninput,anexternalmaster
shouldassertthispintorequest60xbusownershipfromtheinternal
arbiter.
BG
60xBusGrant
I/O
Thisisanoutputwhenaninternalarbiterisusedandaninputwhenan
internalarbiterisused.Asanoutput,thePowerQUICCIIassertsthispin
togrant60xbusownershiptoanexternalbusmaster.Asaninput,an
externalarbitershouldassertthispintogrant60xbusownershiptothe
PowerQUICCII.
ABB
IRQ2
60xAddressBusBusy
I/O
AsanoutputthePowerQUICCIIassertsthispinforthedurationofthe
addressbustenure.FollowinganAACK,whichterminatestheaddress
bustenure,thePowerQUICCIInegatesABBforafractionofabuscycle
andthanstopsdrivingthispin.Asaninput,thePowerQUICCIIwillnot
assume60xbusownership,aslongasitsensesthispinisassertedby
anexternal60xbusmaster.
InterruptRequest2
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
TS
T-S60xBusTransferStart
I/O
Assertionofthispinsignalsthebeginningofanewaddressbustenure.
ThePowerQUICCIIassertsthissignalwhenoneofitsinternal60xbus
masters(core,dma,PCIbridge)beginsanaddresstenure.Whenthe
PowerQUICCIIsensesthispinbeingassertedbyanexternal60xbus
master,itwillrespondtotheaddressbustenureasrequired(snoopif
enabled,accessinternalPowerQUICCIIresourcesandmemory
controllersupport).
A[0:31]
60xAddressBus
I/O
WhenthePowerQUICCIIisintheexternalmasterbusmode,thesepins
functionasthe60xaddressbus.ThePowerQUICCIIdrivestheaddress
ofitsinternal60xbusmastersandwillrespondtoaddressesgenerated
byexternal60xbusmasters.WhenthePowerQUICCIIisintheinternal
masterbusmode,thesepinsareusedasaddresslinesconnectedto
memorydevicesandcontrolledbythePowerQUICCII’smemory
controller.
TT[0:4]
60xBusTransferType
I/O
The60xbusmasterdrivesthesepinsduringtheaddresstenureto
specifythetypeofthetransaction.
TBST
60xBusTransferBurst
I/O
The60xbusmasterassertsthispintoindicatethatthecurrent
transactionisabursttransaction(transfers4doublewords).
TSIZ[0:3]
60xTransferSize
I/O
The60xbusmasterdrivesthesepinswithavalueindicatingtheamount
ofbytestransferredinthecurrenttransaction.
AACK
60xAddressAcknowledge
I/O
A60xbusslaveassertsthissignaltoindicatethatithasidentifiedthe
addresstenure.Assertionofthissignalterminatestheaddresstenure.
ARTRY
60xAddressRetry
I/O
Assertionofthissignalindicatesthatthebustransactionshouldbe
retriedbythe60xbusmaster.ThePowerQUICCIIassertsthissignalto
enforcedatacoherencywithitsinternalcacheandtopreventdeadlock
situations.
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