參數(shù)資料
型號(hào): ORT82G5-3BM680
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝: PLASTIC, BGA-680
文件頁(yè)數(shù): 76/110頁(yè)
文件大?。?/td> 1459K
代理商: ORT82G5-3BM680
68
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 19
. Absolute Maximum Ratings
Recommended Operating Conditions
Table 20
. Recommended Operating Conditions
*For recommended operating conditions for VDDIO, see the Series 4 FPGA Data Sheet and the Series 4 I/O Buffer Application Note.
Designed for greater than 10 year electromigration life at 3.125 Gbits/s at 100 C junction temperature.
SERDES Electrical and Timing Characteristics
Table 21. Absolute Maximum Ratings
Table 22. Recommended Operating Conditions
Note: VDDIB is the center tap of the CML input buffer. In some cases this signal may be left oating, or tied to another voltage level when not
interfacing to CML output buffers. See the SERDES CML Buffer Interface Application note for details.
Parameter
Symbol
Min
Max
Unit
Storage Temperature
Tstg
– 65
150
°C
Power Supply Voltage with Respect to Ground
VDD33
– 0.3
4.2
V
VDDIO
– 0.3
4.2
V
VDD15
—2
V
Input Signal with Respect to Ground
VIN
VSS – 0.3
VDDIO + 0.3
V
Signal Applied to High-impedance Output
VSS – 0.3
VDDIO + 0.3
V
Maximum Package Body Temperature
220
°C
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage with Respect to Ground*
VDD33
2.7
3.6
V
VDD15
1.4
1.6
V
Input Voltages
VIN
VSS – 0.3
VDDIO + 0.3
V
Junction Temperature
TJ
– 40
125
°C
Parameter
Conditions
Min
Typ
Max
Unit
Power Dissipation
SERDES, MUX/deMUX, Align FIFO, and I/O (per channel)
225
mW
8b/10b encoder/decoder (per channel)
50
mW
Parameter
Conditions
Min
Typ
Max
Unit
VDD15 Supply Voltage (VDD15, VDDRx, VDDTx, VDDAUX, VDDGB)
1.425
1.575
V
CML I/O Supply Voltage (VDDIB, VDDOB)
1.425
1.890
V
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