參數(shù)資料
型號： ORT82G5-3BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 69/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-3BM680
Lattice Semiconductor
61
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Clocking Recommendations for
ORT82G5 (continued)
On-board Clocking Strategies
The clocking diagrams shown in Figure 21 and Figure
23 involve the following:
■
There are 2 clocks to the receive alignment fos
within a quad. Every twin within a quad can have a
separate clock (Figure 21). These clocks are
RSYS_CLK_A1 and RSYS_CLK_A2 for quad A
which are used by channel pairs AA,AB and AC,AD
respectively. RSYS_CLK_B1 and RSYS_CLK_B2
are clocks in quad B which are used by channel pairs
BA,BB and BC,BD respectively.
■
Every transmit channel has its own independent
77.76 MHz clock from FPGA to the low-speed MUX
in the core. These clocks are TSYS_CLK_[AA, AB,
. . . BD] as shown in Figure 23.
This enables the following clocking possibilities:
■
All Rx and Tx channels within a quad can be used
when channel alignment feature is enabled.
■
In Rx channel alignment bypass mode, each receive
channel operates on its own low speed clock domain
RWCKxx. Note that the Rx alignment FIFO per chan-
nel cannot be used in this mode.
■
When Rx twin-channel alignment is enabled, both
twins within a quad can be sourced by clocks that are
different from the other channels, but each pair of
SERDES in Rx twin alignment must have the same
clock, as shown in Figure 26. RSYS_CLK_A1 can be
sourced from either RWCKAA or RWCKAB. For
example, channel pairs AA and AB can be sourced
from a work port card and channel pairs AC and AD
can be sourced from a protect port card. Each of
these port cards have their own local reference clock.
■
For Rx quad alignment, RSYS_CLK_[A1,B1] and
RSYS_CLK_[A2,B2] can be tied together as shown
for quad A and B in Figure 25.
■
In Rx eight-channel alignment, either RCK78A or
RCK78B can be used to source RSYS_CLK_[A1,A2]
and RSYS_CLK_[B1,B2] as shown in Figure 27.
■
For Tx, TSYS_CLK_A[A:D] can be sourced by
TCK78A and TSYS_CLK_B[A:D] can be sourced by
TCK78B if the same transmit line rate exists for all 4
channels in a quad.
■
If the transmit line rate is mixed between half and full-
rate among the channels, then the scheme shown in
Figure 24 can be used. The gure shows
TSYS_CLK_AA being sourced by TCK78A and
TSYS_CLK_AB being sourced by TCK78A/2 (the
division is done in FPGA logic).
■
In the Rx path, the channel alignment bypass mode
allows mixing of half and full line rates among the 8
channels. The eight RWCKxx clock signals can be
used to clock low speed receive data from the
respective channel xx. Note that the Rx alignment
FIFO per channel cannot be used in this mode.
■
In Rx channel alignment mode, there are two levels
of inputs that lead to multiple possibilities:
— Each twin can be congured either in half-rate or
full-rate mode as shown in Figure 22. The gure
shows channel pair AA and AB congured in full-
rate mode at 2.0 Gbits/s. This pair is sourced on
the low speed side by RSYS_CLK_A1. Either
RWCKAA or RWCKAB can be connected to
RSYS_CLK_A1. Channel pair AC and AD are
congure in half-rate mode at 1.0 Gbits/s and are
sourced on the low speed side by
RSYS_CLK_A2. Either RWCKAC or RWCKAD
can be connected to RSYS_CLK_A2.
— In addition each quad can be congured in any
line rate (1.0—3.5 Gbits/s), since each quad has
its own reference clock input pins.
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