參數(shù)資料
型號(hào)： ORT82G5-3BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 19/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-3BM680
16
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
Reset Operation
The SERDES block can be reset in one of three differ-
ent ways as follows: on power up, using the hardware
reset, or via the microprocessor interface. The power
up reset process begins when the power supply volt-
age ramps up to approximately 80% of the nominal
value of 1.5 V. Following this event, the device will be
ready for normal operation after 3 ms.
A hardware reset is initiated by making the
PASB_RESETN low for at least two microprocessor
clock cycles. The device will be ready for operation
3 ms after the low to high transition of the
PASB_RESETN. This reset function affects all SER-
DES channels and resets all microprocessor and inter-
nal registers and counters.
Using the software reset option, each channel can be
individually reset by setting SWRST (bit 2) to a logic 1
in the channel conguration register. The device will be
ready 3 ms after the SWRST bit is deasserted. Simi-
larly, all four channels per quad SERDES can be reset
by setting the global reset bit GSWRST. The device will
be ready for normal operation 3 ms after the GSWRST
bit is deasserted. Note that the software reset option
resets only SERDES internal registers and counters.
The microprocessor registers are not affected. It should
also be noted that the embedded block cannot be
accessed until after FPGA conguration is complete.
Start Up Sequence
The following sequence is required by the ORT82G5
device. For information required for simulation that may
be different than this sequence, see the ORT82G5
design kit.
1. Initiate a hardware reset by making
PASB_RESETN low. Keep this low during FPGA
conguration of the device. The device will be
ready for operation 3 ms after the low to high tran-
sition of PASB_RESETN.
2. Congure the following SERDES internal and
external registers. Note that after device initializa-
tion, all alarm and status bits should be read once
to clear them. A subsequent read will provide the
valid state. Set the following bits in register
30800:
— Bits LCKREFN_[AD:AA] to 1, which implies
lock to data.
— Bits ENBYSYNC_[AD:AA] to 1 which enables
dynamic alignment to comma.
Set the following bits in register 30801:
— Bits LOOPENB_[AD:AA] to 1 if high-speed
serial loopback is desired.
Set the following bits in register 30900:
— Bits LCKREFN_[BD:BA] to 1 which implies
lock to data.
— Bits ENBYSYNC_[BD:BA] to 1 which enables
dynamic alignment to comma.
Set the following bits in register 30901:
— Bits LOOPENB_[BD:BA] to 1 if high-speed
serial loopback is desired.
Set the following bits in registers 30002, 30012,
30022, 30032, 30102, 30112, 30122, 30132:
— TXHR set to 1 if TX half-rate is desired.
— 8B10BT set to 1
Set the following bits in registers 30003, 30013,
30023, 30033, 30103, 30113, 30123, 30133:
— RXHR Set to 1 if RX half-rate is desired.
— 8B10BR set to 1.
Assert GSWRST bit by writing two 1’s. Deassert
GSWRST bit by writing two 0’s.
Wait 3ms. If higher speed serial loopback has
been selected, the receive PLLs will use this time
to lock to the new serial data.
Monitor the following alarm bits in registers
30000, 30010, 30020, 30030, 30110, 30120,
30130:
— LKI-PLL lock indicator. 1 indicates that PLL
has achieved lock.
3. If 8b/10b mode is enabled, enable link synchroni-
zation by sending the following sequence three
times:
— K28.5 D21.4 D21.5 D21.5
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