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參數(shù)資料
| 型號(hào)： | ORT82G5-3BM680 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, BGA-680 |
| 文件頁數(shù)： | 21/110頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | ORT82G5-3BM680 |
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18
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed Description (continued)
SERDES Transmit Path (FPGA
→ Backplane)
The transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port from
the MUX/deMUX block. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to
synthesize the internal high-speed serial bit clock.
The serialized data are available at the differential CML output terminated in 50 or 75 to drive either an optical
transmitter, coaxial media, or circuit board/backplane.
Each channel includes a PRBS generator that is available for various test capabilities on the device.
The STBDx[8:0] (where x is a placeholder for one of the letters, A—D) ports carry unencoded character data in this
design. The time-division multiplexer in the ORT82G5 is only 9 bits wide. The 10th bit (STBDx[9]) of each data lane
into the SERDES is held constant. It is not possible to use the ORT82G5 for normal data communication without
enabling SERDES 8b/10b encoding.
The functional mode uses the STBCx311 SERDES output as the reference clock. The frequency of this clock will
depend on the half-rate/full-rate control bit in the SERDES; and the frequency of the REFCLK ports and/or that of
the high-speed serial data. The SERDES TBCKSEL control bit must be congured to a 0 for each channel in order
for this clocking strategy to work.
A falling edge on the STBC311x clock port will cause a new data character to be sent from STBDx[9:0] to the SER-
DES block with a latency of 5 STBC311x clock cycles at the high-speed serial output.
2264(F)
Figure 4. ORT82G5 Transmit Path for a Single SERDES Channel
10:1
MULTIPLEXER
100—175 MHZ
PLL
8B/10B
ENCODER
CLOCK
TRANSMIT DATA
1.0—3.5 Gbits/s
4:1
MULTIPLEXER
(X 9)
10
8
REFERENCE
EMBEDDED CORE
DATA BYTE
STBDx[7:0]
K-CONTROL
STBDx{8]
9
GROUND
STBDx[9]
STBC311x
SERDES
MUX/DEMUX
HDOUTPx,
HDOUTNx
.....
pq
r
s
t
x
y
z
STBDx[9:0]
.....
STBC311x
.....
HDOUTx
p
4
p
5
p
6
p
7
p
8
p
9
p
0
p
1
p
2
p
3
LATENCY =
5 STBC311x CLOCKS
BLOCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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