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參數(shù)資料
| 型號： | ORT82G5-3BM680 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, BGA-680 |
| 文件頁數(shù)： | 15/110頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | ORT82G5-3BM680 |
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12
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
ORT82G5 Overview
Device Layout
The ORT82G5 is a backplane transceiver FPSC with embedded CDR and SERDES circuitry and 8b/10b encoding/
decoding (IEEE 802.3z). It is intended for high-speed serial backplane data transmission. Built using Series 4
recongurable system-on-chips (SoC) architecture, it also contains up to 400k usable FPGA system gates.
The ORT82G5 contains an FPGA base array, an eight-channel clock and data recovery macro, and an eight-chan-
nel 8b/10b interface on a single monolithic chip.
Figure 1 shows the ORT82G5 block diagram. Boundary scan for the ORT82G5 only includes programmable I/Os
and does not include any of the embedded block I/Os.
Backplane Transceiver Interface
The ORT82G5 backplane transceiver FPSC has eight channels, each operating at up to 3.125 Gbits/s
(2.5 Gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The CDR macro
with 8b/10b provides guaranteed ones density for the CDR, byte alignment, and error detection.
The CDR interface provides a physical medium for high-speed asynchronous serial data transfer between system
devices. Devices can be on the same PC-board, on separate boards connected across a backplane, or connected
by cables. This core is intended for, but not limited to, terminal equipment in SONET/SDH, Gbit Ethernet, 10 Gbit
Ethernet, ATM, bre-channel, and Inniband systems.
The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-
speed (up to 3.5 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each
channel to retime the data, then demultiplexes down to parallel bytes and clock. The transmitter operates in the
reverse direction. Parallel bytes are multiplexed up to 3.5 Gbits/s serial data for off-chip communication. The trans-
mitter generates the necessary 3.5 GHz clocks for operation from a lower speed reference clock.
This device will support 8b/10b encoding/decoding, which is capable of frame synchronization and physical link
monitoring. Figure 2 shows the internal architecture of the ORT82G5 backplane transceiver core.
1023(F)
Figure 1. ORT82G5 Block Diagram
STANDARD
ORCA
SERIES 4
FPGA LOGIC
CLOCK/DATA
RECOVERY
BYTE-
WIDE
DATA
CML
8 FULL-
3.5 Gbits/s
FPGA I/Os
DATA
DUPLEX
SERIAL
CHANNELS
I/Os
8b/10b
TO
1.0 Gbits/s
3.5 Gbits/s
DATA
TO
1.0 Gbits/s
DECODER/ENCODER
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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