參數(shù)資料
型號(hào)： ORT82G5-3BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁(yè)數(shù)： 40/110頁(yè)
文件大?。?/td> 1459K
代理商： ORT82G5-3BM680
Lattice Semiconductor
35
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed Description (continued)
Note that any channel within an alignment group can be removed from that alignment group by setting
FMPU_STR_EN_XX to 0. The disabling of any channel(s) within an alignment group will not affect the operation of
the remaining active channels. If the active channels are synchronized, that synchronization will be maintained and
no data loss will occur.
Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices
needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from
a second alignment FIFO until all channels requesting alignment on the current device AND all channels request-
ing alignment on the other device are aligned (as indicated on the K_CTRL character). This second alignment
FIFO will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for
both devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column. Fig-
ure 2 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that
at least ± 80 bits of skew compensation capability should be provided, which the ORT82G5 signicantly exceeds.
2392(F)
Figure 15. Deskew Lanes by Aligning /A/ Columns
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be congured at the
same rate. For example, channels AA, AB, can be congured for twin alignment and full-rate mode, while channels
AC, AD that form an alignment group can be congured for half-rate mode. In quad alignment mode, each receive
quad can be congured in either half or full-rate mode.
When channel alignment is disabled (this control bit NOCHALGNX is available per quad) within a quad, any
receive channel within the quad can be used in half-rate or full-rate mode. The clocking strategy for half-rate mode
in both scenarios- (channel alignment enabled and disabled) is described in section Clocking Recommendations of
ORT82G5.
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs
ORT82G5-3F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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