參數(shù)資料
型號： ORT82G5-3BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 35/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-3BM680
30
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
5-8577 (F)
Figure 10. Interconnect of Streams for FIFO
Alignment
Multichannel Alignment (Backplane
→
FPGA)
The alignment FIFO allows the transfer of all data to
the system clock. The FIFO sync block (Figure 10)
allows the system to be congured to allow the frame
alignment of multiple slightly varying data streams. This
optional alignment ensures that matching SERDES
streams will arrive at the FPGA end in perfect data
sync.
The ORT82G5 has a total of 8 channels (4 per SER-
DES). The incoming data of these channels can be
synchronized in several ways, or they can be indepen-
dent of one other. For example, all four channels in a
SERDES can be aligned together to form a communi-
cation channel with a bandwidth of 10 Gbits/s as shown
Optionally, the alignment can be extended across SER-
DES to align all 8 channels in ORT82G5 as shown in
Figure 12. Individual channels within an alignment
group can be disabled (i.e., power down) without dis-
rupting other channels.
Alternatively, two channels within a SERDES can be
aligned together; channel A and B and/or channel C
and D can form a pair as shown in Figure 13.
0673(F)
Figure 11. Example of SERDES A Alignment and
SERDES B Alignment
0674
Figure 12. Example of SERDES A and B Alignment
Note: Streams A and B of SERDES B are not aligned.
0675
Figure 13. Example of Multiple Twin Channel
Alignment
SERDES A
STREAM A
SERDES A
STREAM B
SERDES A
STREAM C
SERDES A
STREAM D
SERDES B
STREAM A
SERDES B
STREAM B
SERDES B
STREAM C
FIFO
SYNC
SERDES B
STREAM D
SERDES A
SERDES B
SERDES A Stream A
ALL 4 ALIGNMENT OF SERDES A AND SERDES B
t0
t1
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
SERDES A Stream A
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
ALL 8 ALIGNMENT OF SERDES A AND SERDES B
t0
SERDES A Stream A
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
SERDES A Stream A
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
TWO CHANNEL ALIGNMENT
t1 t2
SERDES A Stream A
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
t0
SERDES B Stream D
SERDES B Stream C
SERDES B Stream B
SERDES B Stream A
SERDES A Stream A
SERDES A Stream B
SERDES A Stream C
SERDES A Stream D
TWIN ALIGNMENT OF STREAM A & B OF SERDES A
TWIN ALIGNMENT OF STREAM C & D OF SERDES A
TWIN ALIGNMENT OF STREAM C & D OF SERDES B
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相關代理商/技術參數(shù)
參數(shù)描述
ORT82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs
ORT82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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