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參數資料
| 型號： | ORT82G5-3BM680 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, BGA-680 |
| 文件頁數： | 44/110頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | ORT82G5-3BM680 |
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Lattice Semiconductor
39
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
Operational Mode Full Loopback Test Using The
PRBS Generator/Checker
The operational mode full loopback test forms one of
the normal operational modes of the device. The loop-
back can be either internal to the device or external to
it. To perform the test with internal loopback, the
LOOPENB bit should be set to a logic 1. The test
includes the PRBS generator in the transmit path and
the PRBS checker in the receive path. In this case, the
device is placed in its normal operational mode with all
the functional blocks in the transmit and the receive
path active. The transmit data is generated by an
LFSR. The generated word is then serialized and
looped back (either internally or externally) to the
receiver. The receiver rst deserializes the 8-bit word to
regenerate the transmitted 8-bit word. The PRBS
checker on the receiver compares the regenerated 8-
bit word against the transmitted 8-bit word on a word by
word basis and signals a mismatch by asserting a
PRBSCHK alarm status bit. During this test, the
receiver regenerated 8-bit words can also be observed
on the device output ports. The PRBS checker con-
tains a watchdog timer which asserts the time-out
alarm status bit, PRBSTOUT, if the PRBS test cannot
progress beyond its start state within a reasonable time
interval. This time interval is set by the precision of the
watchdog timer. Both the PRBSCHK and the PRB-
STOUT alarms can generate an interrupt if their corre-
sponding
masks are disabled.
To enable PRBS test, use the following sequence:
■
To preform test with internal loopback, set
LOOPENB bit to 1 (registers 30801, 30901).
■
Set ENBSYNC register bit(s) to 1, depending on the
channel(s) being tested (registers 30800, 30900).
■
Lock receiver to data by setting LCKREFN register
bits to 1 (registers 30800, 30900).
■
Enable PRBS by setting PRBS register bits (30004,
30014, 30024, 30034) (30104, 30114, 30124,
30134). Alternately, the GIPRBS_[A,B] bits can be
used to enable PRBS test for all 4 SERDES chan-
nels within a bank (registers 30005, 30105).
■
Assert GSWRST bit by writing two 1s. Then deassert
the bit by writing two 0s.
■
Monitor DRBSCHK and PRBSTOUT alarm bits.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ORT82G5-3BM680C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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