參數資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數： 8/153頁
文件大?。?/td> 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關產品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
105
30A08
[0]
ALARM_STATUS_BD
00
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[1]
ALARM_STATUS_BC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[2]
ALARM_STATUS_BB
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BB. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[3]
ALARM_STATUS_BA
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BA. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[4]
ALARM_STATUS_AD
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[5]
ALARM_STATUS_AC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[6]
ALARM_STATUS_AB
OR of all alarm status bits for channel AB. A 1
on this bit will set the alarm pin on the system
bus interrupt cause register (on the FPGA side)
Both
[7]
ALARM_STATUS_AA
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AA. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
30A09
[0:7]
B1_ERR_CNT
00
Error counter that increments when a section
B1 error is detected on a link. The link is
selected using ERRCNT_CHSEL. This counter
is cleared on read.
Both
30A0A
[0:7]
CELL_BIP_ERR_CNT
00
Cell BIP Error Counter, Error counter that incre-
ments when a Cell BIP error is detected on a
link. The link being monitored is selected using
ERRCNT_CHSEL. This counter is cleared on
read.
Cell
Table 36. Common Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相關代理商/技術參數
參數描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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