參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 57/153頁
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標(biāo)準(zhǔn)包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關(guān)產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
15
Dual Port RAMs
There are two independent memory blocks in the core. Each memory block has a capacity of 4K words by 36 bits.
It has one read port, one write port, and four byte-write-enable (active-low) signals. The read data from the memory
block is registered so that it works as a pipelined synchronous memory block. These memory blocks are com-
pletely independent of the backplane driver blocks. They are only accessible from the FPGA logic and are not con-
nected to the system bus.
FPSC Conguration - Overview
Conguration of the ORSO42G5 and ORSO82G5 occurs in two stages: FPGA bit stream conguration and
embedded core setup.
Prior to becoming operational, the FPGA goes through a sequence of states, including power-up, initialization, con-
guration, start-up, and operation. The FPGA logic is congured by standard FPGA bit stream conguration means
as discussed in the Series 4 FPGA data sheet.
The options for the embedded core are set via registers that are accessed through the FPGA system bus. The sys-
tem bus can be driven by an external PPC compliant microprocessor via the MPI block or via a user master inter-
face in FPGA logic. A simple IP block, that drives the system by using the user interface and uses very little FPGA
logic, is available in the MPI/System Bus application note (TN1017). This IP block sets up the embedded core via a
state machine and allows the ORSO42G5 and ORSO82G5 to work in an independent system without an external
MicroProcessor Interface.
相關(guān)PDF資料
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EEM22DTAT-S189 CONN EDGECARD 44POS R/A .156 SLD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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