參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 67/153頁
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
20
of differential 0.6 to 2.7 Gbit/s links. At the FPGA/Embedded Core interface, the data are transferred across 32-bit
buses. The SERDES blocks themselves are organized as two blocks. Each of the data paths is identied with a
block and channel identier (i.e., AC, AD, BC, BD or AA,...,BD).
Each channel has a 32-bit TX bus, 32-bit RX bus, a recovered clock, a transmit clock input and a transmit start sig-
nal.
Figure 5. Basic Data Flows - SERDES Only Mode
Figure 6 shows a block diagram of a single channel of the SERDES block. The transmitter section accepts either
scrambled or un-scrambled data at the parallel input port. It also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data are avail-
able at the differential CML output terminated in 86 Ω to drive either an optical transmitter, coaxial media or a circuit
board/backplane.
Figure 6. SERDES Functional Block Diagram for One Channel
Transmit (TX) Path
Receive (RX) Path
Cell
Processing
Pseudo-
SONET
Processing
Configurable
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
Configurable
as
four
or
eight
data
channels
organized
in
two
SERDES
blocks
User
I/O
TX PLL
SERIAL
Output Control
HDOUT P/N
XCK311
MUX
LDIN[7:0]
HAMP
PE
Data
Rate
TXHR
RX PLL
REFCLK P/N
RWCK
LDOUT[7:0]
PARALLEL
RBC
RXHR
LCKREFN
HDIN P/N
NELB
FELB
相關PDF資料
PDF描述
EEM22DTAT-S189 CONN EDGECARD 44POS R/A .156 SLD
ECC20DRES CONN EDGECARD 40POS .100 EYELET
AT-S-26-4/4/W-25-R MOD CORD STANDARD 4-4 WHITE 25'
EEC40DREI CONN EDGECARD 80POS .100 EYELET
0210490869 CABLE JUMPER 1.25MM .203M 17POS
相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*