參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 105/153頁
文件大?。?/td> 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
55
If core FIFO cannot accept cells, cell_begin_ok will be low.
If core FIFO is empty then cell_begin_ok will be asserted every 4 clock cycles until cellvalid is asserted by user
to indicate valid cell data.
cellvalid: Clock-wide pulse asserted by user to indicate valid data. Asserted on the clock cycle following
cell_begin_ok.
Figure 41. ORSO42G5 and ORSO82G5 Transmit FPGA Interface OPC2 Cell Mode
When operating in the eight-link cell mode, the OPC8 block passes user cells from FPGA to embedded core.
Depending upon the congured CELL SIZE, cell transfers will take a variable number of SYSCLK156 cycles to be
transmitted across the interface. Data are always transferred across a 160-bit bus (20 octets per clock cycle).
Figure 42 shows ve clock cycles for a cell transfer this corresponds to a user cell size of 91 octets. The two control
signals in the gure are dened as:
sdo_bp_8: Backpressure signal from core instructing user to stop sending cell data. User should complete trans-
mitting the current cell and can send one more cell before deasserting cellvalid.
cellvalid: Is high throughout a cell transfer to indicate valid cell data
Figure 42. ORSO82G5 Transmit FPGA Interface OPC8 Cell Mode
SYSCLKx[1,2]
cell_begin_ok_x[1,2]
OPC2_x[1,2][39:0]
D
DDD
D
DD
D
DDDD
1 cycle
“n” clk cycles
Cell Size
Clk Cycles
(ocets)
75
79
83
91
16
20
OPC2_x[1,2]_cellvalid
SYSCLK156 8
SDO_BP_8
OPC8[159:0]
D
DDD
D
DD
D
DDDD
“n” clk cycles
Cell Size
Clk Cycles
(ocets)
75
79
83
91
4
5
OPC8_cellvalid
D
“n” clk cycles
相關PDF資料
PDF描述
EEM22DTAT-S189 CONN EDGECARD 44POS R/A .156 SLD
ECC20DRES CONN EDGECARD 40POS .100 EYELET
AT-S-26-4/4/W-25-R MOD CORD STANDARD 4-4 WHITE 25'
EEC40DREI CONN EDGECARD 80POS .100 EYELET
0210490869 CABLE JUMPER 1.25MM .203M 17POS
相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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