參數(shù)資料
型號(hào)： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 147/153頁
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標(biāo)準(zhǔn)包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關(guān)產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
93
Table 31. SERDES Per-Channel Receive Conguration Register Descriptions – ORSO82G5
Table 32. SERDES Common Conguration Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Receive Per-Channel Conguration Registers (Read/Write) xx = [AA,...,BD]
30003 - AA
30013 - AB
30023 - AC
30033 - AD
30103 - BA
30113 - BB
30123 - BC
30133 - BD
[0]
RXHR_xx
20
Receive Half Rate Selection Bit, Channel xx.
When RXHR_xx =1, HDIN_xx's baud rate =
(REFCLK[A:B]*8) and RCK78[A:B]=(REF-
CLK[A:B]/4); When RXHR_xx=0, HDIN_xx's
baud rate = (REFCLK[A:B]*16) and
RCK78[A:B]=(REFCLK/2).
RXHR_xx = 0 on device reset.
Both
[1]
PWRDNR_xx
Receiver Power Down Control Bit, Channel xx.
When PWRDNR_xx = 1, sections of the receive
hardware are powered down. PWRDNR_xx = 0
on device reset.
Both
[2:7]
RSVD
Reserved (Bit 2 = 1 on device reset)
—
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write) xx = [AA,...,BD]
30004 - AA
30014 -AB
30024 - AC
30034 - AD
30104 - BA
30114 - BB
30124 - BC
30134 - BD
[0]
RSVD
40
Reserved
—
[1]
MASK_xx
Transmit and Receive Alarm Mask Bit, Channel
xx. When MASK_xx = 1, the transmit and
receive alarms of a channel are prevented from
generating an alarm (i.e., they are masked or
disabled). The MASK_xx bit overrides the indi-
vidual alarm mask bits in the Alarm Mask Reg-
isters.
MASK_xx = 1 on device reset.
Both
[2]
SWRST_xx
Transmit and Receive Software Reset Bit,
Channel xx. When SWRST_xx = 1, this bit pro-
vides the same function as the hardware reset,
except that all conguration register settings are
unaltered. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared.
SWRST = 0 on device reset.
Both
[3:6]
RSVD
Reserved
—
[7]
TESTEN_xx
Transmit and receive Test Enable Bit, Channel
xx. When TESTEN_xx = 1, the transmit and
receive sections of channel xx are place in test
mode. The TESTMODE_xx bits (30006, 30106,
etc.) must be set to specify the desired test. The
GTESTEN_[A:B] bits override the individual
TESTEN_xx settings.
Both
30006-AA
30016-AB
30026-AC
30036-AD
30106-BA
30116-BB
30126-BC
30136-BD
[0]
TESTMODE_xx
00
SERDES Test Mode Select, channel xx.
TESTMODE_xx = 0 selects Far End Loopback
(CML TX to CML RX internally)
TESTMODE_xx = 1 selects Near End Loopback
(CML RX to CML TX internally)
Factory
Test
[1:7]
RSVD
Reserved, Set to zero (default).
—
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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