參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 20/153頁
文件大?。?/td> 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關產品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
116
This section describes device I/O signals to/from the embedded core.
Table 48. FPSC Function Pin Descriptions
Symbol
I/O
Description
Common Signals for Both SERDES Block A and B
PASB_RESETN
I
Active low reset for the embedded core.
1
PASB_TRISTN
I
Active low 3-state for embedded core output buffers.
1
PASB_PDN
I
Active low power down of all SERDES blocks and associated I/Os.
1
PASB_TESTCLK
I
Clock input for BIST and loopback test (factory only).
1
PBIST_TEST_ENN
I
Selection of PASB_TESTCLK input for BIST test (factory only).
1
PLOOP_TEST_ENN
I
Digital only loopback from TX to RX (factory only).
1
PMP_TESTCLK
I
Clock input for microprocessor in test mode (factory only).
1
PMP_TESTCLK_ENN
I
Selection of PMP_TESTCLK in test mode (factory only).
1
PSYS_DOBISTN
I
Input to start BIST test (factory only).
1
PSYS_RSSIG_ALL
O Output result of BIST test (factory only).
SERDES Block A and B Pins
REFCLKN_A
I
CML reference clock input—SERDES block A.
REFCLKP_A
I
CML reference clock input—SERDES block A.
REFCLKN_B
I
CML reference clock input—SERDES block B.
REFCLKP_B
I
CML reference clock input—SERDES block B.
REXT_A
— Reference resistor—SERDES block A.
REXT_B
— Reference resistor—SERDES block B.
REXTN_A
— Reference resistor – SERDES block. A 3.32 K W ± 1% resistor must be connected across
REXT_B and REXTN_B. This resistor should handle a current of 300 A.
REXTN_B
— Reference resistor—SERDES block B. A 3.32 K Ω ± 1% resistor must be connected across
REXT_B and REXTN_B. This register should handle a current of 300 A
HDINN_AA
I
High-speed CML receive data input—SERDES block A, channel A (not available in ORSO42G5).
HDINP_AA
I
High-speed CML receive data input—SERDES block A, channel A (not available in ORSO42G5).
HDINN_AB
I
High-speed CML receive data input—SERDES block A, channel B (not available in ORSO42G5).
HDINP_AB
I
High-speed CML receive data input—SERDES block A, channel B (not available in ORSO42G5).
HDINN_AC
I
High-speed CML receive data input—SERDES block A, channel C.
HDINP_AC
I
High-speed CML receive data input—SERDES block A, channel C.
HDINN_AD
I
High-speed CML receive data input—SERDES block A, channel D.
HDINP_AD
I
High-speed CML receive data input—SERDES block A, channel D.
HDINN_BA
I
High-speed CML receive data input—SERDES block B, channel A.
HDINP_BA
I
High-speed CML receive data input—SERDES block B, channel A (not available in ORSO42G5).
HDINN_BB
I
High-speed CML receive data input—SERDES block B, channel B (not available in ORSO42G5).
HDINP_BB
I
High-speed CML receive data input—SERDES block B, channel B (not available in ORSO42G5).
HDINN_BC
I
High-speed CML receive data input—SERDES block B, channel C (not available in ORSO42G5).
HDINP_BC
I
High-speed CML receive data input—SERDES block B, channel C.
HDINN_BD
I
High-speed CML receive data input—SERDES block B, channel D.
HDINP_BD
I
High-speed CML receive data input—SERDES block B, channel D.
SERDES Block A and B Pins
HDOUTN_AA
O High-speed CML transmit data output—SERDES Block A, channel A (not available in
ORSO42G5).
HDOUTP_AA
O High-speed CML transmit data output—SERDES Block A, channel A (not available in
ORSO42G5).
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相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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