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參數(shù)資料
| 型號(hào)： | ORSO42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 62/153頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DEV PLATFORM ORSO42G5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORSO42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORSO42G5EV |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
16
ORSO42G5 and ORSO82G5 Embedded Core Detailed Description
The ORSO42G5 and ORSO82G5 have four and eight channels respectively, with a high-speed SERDES macro
that performs clock data recovery, serializing and deserializing functions. There is also additional logic for SONET
mode and cell mode data synchronization formatting and scrambling/descrambling. For all modes, the data paths
can be characterized as the transmit path (FPGA to backplane) and receive path (backplane to FPGA); however
the interface signal assignments between the FPGA logic and the core differ depending on the operating mode
selected.
The three main operating modes in the ORSO42G5 and ORSO82G5 are:
SERDES only mode
SONET mode
Cell mode
– Two-link sub-mode
– Eight-link sub-mode (ORSO82G5 only)
The SONET and cell modes each support sub-modes that can be selected by enabling or disabling certain func-
tions through programmable register bits. Following the basic TX and RX architecture descriptions, the data format-
ting and logical implementations supporting each of the operational modes are described.
Top Level Description - Transmitter (TX) and Receiver (RX) Architectures
The next sections give a top level description of the transmitter and receive architectures. The high-speed transmit
and receive serial data can operate at 0.6-2.7 Gbps depending on the state of the control bits from the system bus
and the provided reference clock. For all of the architecture and clock distribution descriptions, however, the stan-
dard SONET STS-48 rate of 2,488.32 Mbits/s (i.e., REFCLK_[P:N] = 155.52 MHz for the full rate modes) is
assumed.
Transmitter Architecture
The transmitter section accepts parallel data for transmission from the FPGA logic, formats it for transmission and
serializes the data. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to syn-
thesize the internal high-speed serial bit clock. The serialized transmitted data are available at the differential CML
output pins to drive either an optical transmitters, coaxial media or a circuit board backplane.
The top level transmit architecture is shown in Figure 3. The main logical blocks in the transmit path are:
Output Port Controllers (OPCs) which contain the cell processing logic.
SONET processing logic.
Transmit SERDES and 32:8 MUX.
Depending on the mode of operation, the FPGA to backplane data path may include or bypass the various logical
blocks.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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