參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 149/153頁
文件大?。?/td> 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關(guān)產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
95
Table 34. Per-Channel Control Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
30800 - AA
30810 - AB
30820 - AC
30830 - AD
30900 - BA
30910 - BB
30920 - BC
30930 - BD
[0:4]
RSVD
00
Reserved
—
[5]
CELL_ALIGN_ERR_EN_xx
‘1’ = Alarm enabled for CELL_ALIGN_ERR_xx
Cell
[6]
TX_URUN_ERR_EN_xx
‘1’ = Alarm enabled for TX_URUN_ERR_xx
Cell
[7]
TX_ORUN_ERR_EN_xx
‘1’ = Alarm enabled for TX_ORUN_ERR_xx
Cell
30801 - AA
30811 - AB
30821 - AC
30831 - AD
30901 - BA
30911 - BB
30921 - BC
30931 - BD
[0]
RSVD
00
Reserved
—
[1]
OOF_EN_xx
‘1’ = Alarm enabled for OOF_xx
Both
[2]
EX_SEQ_ERR_EN_xx
‘1’ = Alarm enabled for EX_SEQ_ERR _xx
Cell
[3]
SEQ_ERR_EN_xx
‘1’ = Alarm enabled for SEQ_ERR _xx
Cell
[4]
CELL_BIP_ERR_EN_xx
‘1’ = Alarm enabled for CELL_BIP_ERR_xx
Cell
[5]
B1_ERR_EN_xx
‘1’ = Alarm enabled for B1_ERR_xx
Both
[6]
RX_FIFO_OVRUN_EN_xx
‘1’ = Alarm enabled for RX_FIFO_OVRUN_xx
Cell
[7]
RDI_EN_xx
’1’ = Alarm enabled for RDI_xx
Both
30802 - AA
30812 - AB
30822 - AC
30832 - AD
30902 - BA
30912 - BB
30922 - BC
30932 - BD
[0]
ENABLE_JUST_xx
00
ENABLE_JUST_xx =1 causes the core to inter-
pret pointer bytes for positive or negative justi-
cation
SONET
[1]
FMPU_STR_EN_xx
FMPU_STR_EN_xx = 1 enables a channel for
alignment within a multi-channel alignment
group
SONET
[2:3]
FMPU_SYNMODE_xx
“00” - No channel alignment
“01” - Twin channel alignment
“10” - 4 channel alignment
“11 - By-8 alignment
SONET
[4]
DSCR_INH_xx
Descrambling Inhibit, DSCR_INH = 1 inhibits
descrambling (in the Rx direction) and scram-
bling (in the Tx direction). When inhibiting the
scrambler and descrambler the AUTO_B1_xx
calculated and checked B1 value will always be
incorrect.
Both
[5]
FFRM_EN_xx
Fast Frame Enable, FFRM_EN=1 enables the
fast frame mode.
Both
[6]
AIS_ON_xx
Alarm Indication Signal (control), AIS_ON =1
forces AIS-L insertion.
Both
[7]
AIS_ON_OOF_xx
Alarm Indication Signal on Out of Frame,
AIS_ON_OOF =1 forces AIS-L insertion during
OOF =1.
Both
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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