參數(shù)資料
型號(hào): OL2300NHN
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Fractional-N PLL based transmitter
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC16
封裝: 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁數(shù): 28/46頁
文件大小: 951K
代理商: OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
28 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
6.7.10
Transmit data command
6.7.10.1
Transmit configuration
Some transmit-configuration bits must be sent via SPI before every transmit command. (A
to F, see
Figure 20 “Transmit data timing diagram”
).
Other configuration settings are stored in the registers and the state machine retains them
until these bits are altered.
6.7.11
Description of the configuration bits
6.7.11.1
Synchronization
Bit A = 1:
Synchronization of the data at the falling or at the rising edge of SCK with the
baud rate clock (CLK
ASC
) (also dependent of register setting).
Bit A = 0:
No synchronization of the transmit-data.
6.7.11.2
Power amplifier
The power amplifier is always turned on with the ninth nonsignificant edge of SCK.
Configuration bit B is used to turn off the power amplifier.
Bit B = 1:
The power amplifier is turned off after the falling edge of EN (synchronized with
baud rate, if enabled). Data is transmitted after the power amplifier is turned on. During
transmission EN must be kept 1 and the data at SDIO is transmitted transparently or
synchronized with the baud rate.
Bit B = 0:
Data transmission starts after the power amplifier is turned on. With the falling
edge of EN the actual data bit at SDIO is latched and a constant carrier will be transmitted
either in NRZ mode (bit C = 0) or with Manchester coding (bit C = 1) until the power
amplifier is turned off.
6.7.11.3
Data coding
Bit C = 1:
Data is XOR d (Manchester generation) with baud rate clock. If C=1 the value
of ‘A’ will be ignored and the data transmission will be done synchronized to the baud rate
clock.
Bit C = 0:
NRZ mode selected.
6.7.11.4
Modulation and power settings
Bit D = 1:
Modulation and amplitude/power settings of ACON1 are applied (according to
Figure 10
).
Bit D = 0:
Modulation and amplitude/power settings of ACON0 are applied (according to
Figure 10
).
6.7.11.5
Frequency settings
Bits E, F:
Selection of frequency configuration registers.
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