參數(shù)資料
型號: OL2300NHN
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Fractional-N PLL based transmitter
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC16
封裝: 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁數(shù): 23/46頁
文件大?。?/td> 951K
代理商: OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
23 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
6.7.6
Synchronous mode
When operating the device in synchronous mode data is clocked on the rising edge of
CKOUT. It is possible to invert this clock signal as described in
Table 31
. Inverting this
signal has the effect of clocking the data presented at SDIO on the falling edge of CKOUT.
The clock for the data generator has a dedicated afterscaler, therefore the CKOUT signal
can run at a higher frequency if desired, as described in
Table 33
.
6.7.7
General SPI information
The chip is configured via the serial SPI interface, consisting of an 8-bit shift register and
twenty 8-bit registers holding the configuration data.
Data can be exchanged with multiple 8-bit frames (auto increment) or in portions of 8 bits
(1 byte), which could be of advantage if a hardware SPI-interface is used. Data in the shift
register is loaded into the addressed register with the last edge of SCK within the last bit
of the transferred byte.
6.7.7.1
SPI special function register-set
All registers are able to read or write via the SPI communication and are therefore
arranged as a block with 20 addressable bytes.
Some of the bits of the registers indicate the state of the implemented TX state-machine
and can alter without SPI transmission. (e.g. the ‘PD bit’ can be automatically set if EN is
kept low for a number of XTAL clocks pulses or via dedicated SPI communication). Other
bits only can be altered via SPI communication. (e.g. the frequency setting for the baud
rate generator BD[7:0] or the configuration bits for the TX state-machine).
In order to change the operating mode of the transmitter, the special function register bits
PD or PLLEN of register TXCON must be accessed. To change from one state to another
via SPI communication without intermediate states, these state describing bits are
arranged in one byte. The byte will be written after completion of the byte transfer.
All the registers keep the stored information in power-down state but if a dynamic
power-on reset occurs (can be evaluated by checking the PLLEN bit after transmission)
the registers content may change. Only register TXCON is reset to a default state. All
other registers must be reset to ensure proper function after a dynamic reset.
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