參數(shù)資料
型號: OL2300NHN
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡
英文描述: Fractional-N PLL based transmitter
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC16
封裝: 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁數(shù): 20/46頁
文件大?。?/td> 951K
代理商: OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
20 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
6.7 Baud rate generation
6.7.1
Baud rate setting
Different baud rates for the internal transmit data stream generation can be chosen
dependent on the setting of register BDSEL (baud rate selection).
Table 27.
Bit 7
BD7
R/W
The bits BD[7:0] set the division ratio of a programmable frequency divider. The input
clock of this divider is influenced by prescaler ratio PSC[2:0] defined in register SCSEL.
The output of this divider is fed to the baud rate generator (See
Figure 14
).
The prescaler output clock is derived from the reference frequency f
ref
divided by the
prescaler ratio PSC[2:0]. The prescaler clock is then divided by (N+1) (N is the baud rate
setting in the BDSEL register) and again divided by a factor of 2 (See
Figure 14
and
Table 28
).
Fig 14. Serial configuration interface block diagram of baud rate and data generation
2
3
8
001aak392
/ 2
16
RESET
SET
RESET
PRESCALER
RESET
AFTERSCALER
RESET
COUNTER
8 bit
COMPARE
RESET
3
to
1
s[1:0]
3
to
1
INV
EN
latch
EN
''1''
1
powerdown
PAON
powerdown
timer
baudrate
generator
data generator
deglitch FF
data synchronisation
(Bit ''A''; TX-command)
MC
(Bit ''C''; TX-command)
PD (TXCON)
PAON
Clk
PSC
Clk
BD
Clk
ASC
EN
f
REF
CSS2
PAON
CSS1, CSS0
clock source select
PDCK
(TXCON)
LOW
01
00
10
11
BDSEL
BD[7:0]
2
ASC
CKOUT
to SFR interface
enter TX-state (command)
SDIO
PSC
XOR
f
REF
TX data
s0
00
01
1
×
s1
PAON
Address 0Fh; BDSEL, baud rate selection
Bit 6
Bit 5
BD6
BD7
R/W
R/W
Bit 4
BD4
R/W
Bit 3
BD3
R/W
Bit 2
BD2
R/W
Bit 1
BD1
R/W
Bit 0
BD0
R/W
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