參數(shù)資料
型號: OL2300NHN
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Fractional-N PLL based transmitter
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC16
封裝: 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁數(shù): 15/46頁
文件大小: 951K
代理商: OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
15 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
Table 14.
Bit 7
[1]
MRCON is also used for soft-FSK.
The configured ramp time also defines the maximum possible data rate for ASK
operation. The ramp time can be calculated by:
(4)
For RMP0 to RMP6 is not equal to 0, the maximum baud rate is given by:
(5)
For RMP0 to RMP6 is equal to 0 (normal ASK mode), the maximum baud rate is only
limited by the baud rate generator (see
Section 6.1.4
) and the maximum channel
bandwidth.
6.4.5
CASC, cascode control signal
For a further improvement of the supply voltage stability also for high power modes, the
cascode stage can be switched to the regulated power supply by setting bit CASC located
in register ACON2. Note that the maximum output power is then reduced compared to the
maximum available power in power-mode 3.
Table 15.
CASC
0
1
6.4.6
Voltage regulation and power fail detection
The integrated line regulator supports two different operation modes. The default mode is
called ‘fixed low’ mode where the regulated supply voltage is derived from an internal,
transistor threshold voltage based reference. After start-up of the PLL the second mode
called adaptive mode can be entered by setting the SFR bit ENRAD.
6.4.7
ENRAD, enable regulator adaptive mode
If set, the line regulator is switched to adaptive mode where the output voltage at VREG is
directly derived from the VCOs power supply.
Remark:
ENRAD must not be set until the PLL start-up has finished. It is strongly
recommended to use the fixed mode during PLL start-up.
Table 16.
ENRAD
0
1
Address 0Dh; MRCON, modulation ramp control
[1]
Bit 6
Bit 5
RMP6
RMP5
R/W
R/W
Bit 4
RMP4
R/W
Bit 3
RMP3
R/W
Bit 2
RMP2
R/W
Bit 1
RMP1
R/W
Bit 0
RMP0
R/W
X
R/W
t
SASK
AMH
AML
(
)
f
ref
------
×
MRCON 6:0
]
×
=
f
DATA
SASKmax
t
SASK
2
×
---------------------
=
Cascode control flag (CASC)
Cascode control state
Cascode stage switched to V
DD
Cascode stage switched to V
DDA
(regulated)
Voltage regulator control (ENRAD)
Voltage regulator state
fixed output voltage, derived from internal reference
adaptive mode: regulated supply derived from VCO supply voltage
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