參數(shù)資料
型號(hào)： OL2300NHN
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Fractional-N PLL based transmitter
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC16
封裝： 3 X 3 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT758-1, VQFN-16
文件頁(yè)數(shù)： 21/46頁(yè)
文件大?。?/td> 951K
代理商： OL2300NHN
OL2300
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
21 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
The baud rate division ratio is:
Remark:
For synchronization reasons both baud rate counter and afterscaler are kept in
reset state while the power amplifier is turned off. The prescaler will be clocked
continuously whenever the XTAL oscillator is running.
Table 28.
BD7
0
0
0
6.7.2
Clock generation/selection
The special function register SCSEL contains the configuration bits CSS[2:0] for the clock
source selection, the bits PSC[2:0] for the prescaler control and ASC[2:0] for the
afterscaler control.
Table 29.
Bit 7
CSS2
R/W
The bit PDCK in the TXCON register determines the activity of the CKOUT signal. If
PDCK is cleared, CKOUT will be active.
Table 30.
Bit 7
PD
R/W
CKOUT is defined with the settings of CSS[2:0] from register SCSEL and can be
configured as prescaler output or baud rate output (See
Table 31
).
If CSS2 is cleared then CKOUT is set to baud rate, prescaler or static high or low,
dependent on CSS1 and CSS0 settings if transmit state is active and set to 3-state if
transmission is inactive.
If CSS2 is set then CKOUT is set according to the configuration of CSS1 and CSS0 and
3-state mode is not entered during transmission.
Table 31.
CSS2
0
0
0
0
1
Baud rate division ratio values
BD6
BD5
BD4
0
0
0
0
0
0
0
0
0
BD3
0
0
0
BD2
0
0
0
BD1
0
0
1
BD0
0
1
0
Baud rate division ratio: N
0
1
2
....
255
1
1
1
1
1
1
1
1
CLK
BD
CLK
N
(
×
2
1
+
)
--------------------------
=
Address 10h; SCSEL, scaler selection
Bit 6
Bit 5
CSS1
CSS0
R/W
R/W
Bit 4
PSC2
R/W
Bit 3
PSC1
R/W
Bit 2
PSC0
R/W
Bit 1
ASC1
R/W
Bit 0
ASC0
R/W
Address 0Eh; TXCON, transmitter control
Bit 6
Bit 5
PDCK
XOSL
R/W
R/W
Bit 4
FBSL
R/W
Bit 3
PAM1
R/W
Bit 2
PAM0
R/W
Bit 1
ENXR
R/W
Bit 0
PLLEN
R/W
Clock Source Selection (CSS)
CSS1
CSS0
0
0
0
1
1
0
1
1
0
0
CKOUT
3-state if TX disabled; LOW if TX enabled
3-state if TX disabled; prescaler clock if TX enabled
3-state if TX disabled; baud rate clock if TX enabled
3-state if TX disabled; inverted baud rate if TX enabled
LOW
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