參數資料
型號： NT5DS64M8BF-6KI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 1 MM PITCH, WBGA-60
文件頁數： 60/79頁
文件大?。?/td> 6238K
代理商： NT5DS64M8BF-6KI
NT5DS128M4BF
NT5DS128M4BT
NT5DS128M4BG
NT5DS128M4BS
NT5DS64M8BF
NT5DS64M8BT
NT5DS64M8BG
NT5DS64M8BS
NT5DS32M16BF
NT5DS32M16BT
NT5DS32M16BG
NT5DS32M16BS
512Mb DDR SDRAM
REV 1.3
11/2007
63
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew
rate is below 0.5 V/ns.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate
is below 0.5 V/ns.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS
slew rates differ.
Input Slew Rate
delta (tIS)
delta (tIH)
Unit
Notes
0.5 V/ns
0
ps
1,2
0.4 V/ns
+50
0
ps
1,2
0.3 V/ns
+100
0
ps
1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Input Slew Rate
delta (tDS)
delta (tDH)
Unit
Notes
0.5 V/ns
0
ps
1,2
0.4 V/ns
+75
ps
1,2
0.3 V/ns
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Input Slew Rate
delta (tDS)
delta (tDH)
Unit
Notes
0.0 V/ns
0
ps
1,2,3,4
0.25 V/ns
+50
ps
1,2,3,4
0.5 V/ns
+100
ps
1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
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