參數(shù)資料
型號(hào)： NT5DS64M8BF-6KI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 1 MM PITCH, WBGA-60
文件頁(yè)數(shù)： 2/79頁(yè)
文件大小： 6238K
代理商： NT5DS64M8BF-6KI
NT5DS128M4BF
NT5DS128M4BT
NT5DS128M4BG
NT5DS128M4BS
NT5DS64M8BF
NT5DS64M8BT
NT5DS64M8BG
NT5DS64M8BS
NT5DS32M16BF
NT5DS32M16BT
NT5DS32M16BG
NT5DS32M16BS
512Mb DDR SDRAM
REV 1.3
11/2007
10
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Initialization:
No power sequencing is specified during power up or power down given the following criteria
:
VDD and VDDQ are driven from a single power converter output, AND
VTT meets the specification, AND
VREF tracks VDDQ /2
or
The following relationships must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V, AND
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V, AND
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After
all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200
s delay prior to
applying an executable command.
Once the 200
s delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.
Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be
issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode
Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state
Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode
Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base
or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or
extended mode register can be modified at any valid time during device operation without affecting the state of the internal
address refresh counters used for device refresh.
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