參數(shù)資料
型號(hào)： NT5DS64M8BF-6KI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 1 MM PITCH, WBGA-60
文件頁(yè)數(shù)： 3/79頁(yè)
文件大小： 6238K
代理商： NT5DS64M8BF-6KI
NT5DS128M4BF
NT5DS128M4BT
NT5DS128M4BG
NT5DS128M4BS
NT5DS64M8BF
NT5DS64M8BT
NT5DS64M8BG
NT5DS64M8BS
NT5DS32M16BF
NT5DS32M16BT
NT5DS32M16BG
NT5DS32M16BS
512Mb DDR SDRAM
REV 1.3
11/2007
11
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of
a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register
Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the
CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements results in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length
determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths
of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when
the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining
(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both Read and Write bursts.
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