參數(shù)資料
型號(hào)： NT5DS64M8BF-6KI
廠(chǎng)商： NANYA TECHNOLOGY CORP
元件分類(lèi)： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 1 MM PITCH, WBGA-60
文件頁(yè)數(shù)： 55/79頁(yè)
文件大?。?/td> 6238K
代理商： NT5DS64M8BF-6KI
NT5DS128M4BF
NT5DS128M4BT
NT5DS128M4BG
NT5DS128M4BS
NT5DS64M8BF
NT5DS64M8BT
NT5DS64M8BG
NT5DS64M8BS
NT5DS32M16BF
NT5DS32M16BT
NT5DS32M16BG
NT5DS32M16BS
512Mb DDR SDRAM
REV 1.3
11/2007
59
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Input Operating Conditions
(VDD = VDDQ = 2.6V ± 0.1V; See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
VIH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VREF + 0.31
V
1, 2
VIL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VREF 0.31
V
1, 2
VID(AC)
Input Differential Voltage, CK and CK Inputs
0.62
VDDQ + 0.6
V
1, 2, 3
VIX(AC)
Input Crossing Point Voltage, CK and CK Inputs
0.5*VDDQ 0.2 0.5*VDDQ + 0.2
V
1, 2, 4
1. Input slew rate = 1V/ns
.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions
(VDD = VDDQ = 2.6V ± 0.1V ; See AC Characteristics)
Symbol
Parameter/Condition
DDR400
(5TI)
tCK=5ns
DDR333
(6KI)
tCK=6ns
Unit Notes
IDD0
Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM,
and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
110
105
mA
1
IDD1
Operating Current: one bank; active / read / precharge; Burst = 2; tRC =
tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once
per clock cycle
105
100
mA
1
IDD2P
Precharge Power Down Standby Current: all banks idle; Power Down
mode; CKE
≤ VIL (max)
6
5
mA
1
IDD2N
Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);
address and control inputs changing once per clock cycle
28
25
mA
1
IDD3P
Active Power Down Standby Current: one bank active; Power Down
mode;
CKE
≤ VIL (max)
13
12
mA
1
IDD3N
Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);
CKE
≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock
cycle
50
45
mA
1
IDD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; IOUT = 0mA
125
105
mA
1
IDD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL = 2.5
135
120
mA
1
IDD5
Auto-Refresh Current: tRC = tRFC (min)
210
205
mA
1
IDD6
Self-Refresh Current: CKE ≤ 0.2V
5
mA 1, 2
IDD7
Operating current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every trans-
fer;
t RC = t RC (min); I OUT = 0mA.
390
300
mA
1
1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
Values are averaged from high and low temp values using x16 devices.
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