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參數(shù)資料
| 型號(hào)： | MX53L06402L-50 |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | PROM |
| 英文描述： | FLASH 2.7V PROM CARD, XMA7 |
| 封裝： | CRAD-7 |
| 文件頁數(shù)： | 25/55頁 |
| 文件大?。?/td> | 262K |
| 代理商： | MX53L06402L-50 |
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31
P/N: PM1043
REV. 1.0, NOV. 25, 2003
MX53L06402
7.5.5 Reset Sequence
The MultiMediaCard requires a defined reset sequence. After power on reset or CMD0 (software reset) the card enters
an idle state. At this state the only legal host commands are CMD1 (SEND_OP_COND) and CMD58 (READ_OCR).
The host must poll the card (by repeatedly sending CMD1) until the "in-idle-state" bit in the card response indicates
(by being set to 0) that the card has completed its initialization processes and is ready for the next command.
In SPI mode, as opposed to MultiMediaCard mode, CMD1 has no operands and does not return the contents of the
OCR register. Instead, the host may use CMD58 (available in SPI mode only) to read the OCR register. Furthermore,
it is in the responsibility of the host to refrain from accessing cards that do not support its voltage range.
The usage of CMD58 is not restricted to the initializing phase only, but can be issued at any time. The host must poll
the card (by repeatedly sending CMD1) until the "in-idle-state " bit in the card response indicates (by being set to 0)
that the card has completed its initialization processes and is ready for the next command.
7.5.6 Clock Control
The SPI bus clock signal can be used by the SPI host to set the cards to energy saving mode or to control the data
flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to change the clock frequency or shut
it down.
There are a few restrictions the SPI host must follow:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency,
defined by the MultiMediaCards
It is an obvious requirement that the clock must be running for the MultiMediaCard to output data or response
tokens. After the last SPI bus transaction, the host is required, to provide 8 (eight) clock cycles for the card to
complete the operation before shutting down the clock. throughout this 8 clocks period the state of the CS signal
is irrelevant. it can be asserted or de-asserted.
Following is a list of the various SPI bus transactions:
A command / response sequence. 8 clocks after the card response end bit. The CS signal can be asserted or
de-asserted during these 8 clocks.
A read data transaction. 8 clocks after the end bit of the last data block.
7.5.7 Error Conditions
CRC and Illegal Command
All commands are (optionally) protected by CRC (cyclic redundancy check) bits. If the addressed MultiMediaCard's
CRC check fails, the COM_CRC_ERROR bit will be set in the card's response. Similarly, if an illegal command has
been received the ILLEGAL_COMMAND bit will be set in the card's response.
There are different kinds of illegal commands:
Commands which belong to classes not supported by the MultiMediaCard (e.g. interrupt and I/O commands).
Commands not allowed in SPI mode (e.g. CMD20 - write stream)
Commands which are not defined (e.g. CMD6).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MX54-3 | 功能描述:CUTTER SIDE OVAL FLUSH 4.25" RoHS:是 類別:工具 >> 切割機(jī) 系列:STUSA 標(biāo)準(zhǔn)包裝:1 系列:Xcelite® 類型:側(cè)面（對(duì)角） 形狀:錐形 切邊:凹槽 長度 - 總體:5.00"（127mm） 特點(diǎn):安全夾 容量:20 AWG 軟線 重量:0.2 磅（90.72g） |
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| MX54-9 | 功能描述:CUTTER SIDE OVAL FLUSH 4.25" RoHS:是 類別:工具 >> 切割機(jī) 系列:STUSA 標(biāo)準(zhǔn)包裝:1 系列:Xcelite® 類型:側(cè)面（對(duì)角） 形狀:錐形 切邊:凹槽 長度 - 總體:5.00"（127mm） 特點(diǎn):安全夾 容量:20 AWG 軟線 重量:0.2 磅（90.72g） |
| MX54S30J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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