參數(shù)資料
型號(hào)： MX53L06402L-50
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： PROM
英文描述： FLASH 2.7V PROM CARD, XMA7
封裝： CRAD-7
文件頁(yè)數(shù)： 15/55頁(yè)
文件大?。?/td> 262K
代理商： MX53L06402L-50
22
P/N: PM1043
REV. 1.0, NOV. 25, 2003
MX53L06402
6.7 Command and response timings
All timing diagrams use the following schematics and abbreviations:
Table 19: Timing diagram symbols
S
Start bit (= 0)
T
Transmitter bit (Host = 1, Card = 0)
P
One-cycle pull-up (= 1)
E
End bit (=1)
Z
high impedance state (-> = 1)
D
Data bits
*
repeater
CRC
Cyclic redundancy check bits (7 bits)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card respectively host output
driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R
CMD respectively R DAT . Actively-
driven P-bits are less sensitive to noise superposition.
For the timing of the MX53L06402 the following values are defined:
Min
Max
Description
N
CR
2
64
Number of cycles between command and response
N
ID
5
Number of cycles between card identification or card operation
conditions com-mand and the correspond-ing response.
N
AC
2
TAAC+NSAC
N
BAC
8
Number of cycles between blocks in multiple block read
N
RC
8-
N
CC
8
-
Number of cycles between two commands, if no response will be
sent after the first command (e.g.broadcast)
N
ST
2
Number of cycles between stop command and high Z on DAT
line.
Table 20: Timing values
The host command and the card response are clocked out with the rising edge of the host clock.The delay between
host command and card response is N
CR clock cycles.
The following timing diagram is relevant for host command CMD3:
S
T
content
CRC
E
CMD
Host command
NCR cycles
Response
S
T
content
CRC
E
Z
* * * * * *
Z
Figure 6: Command response timing (identification mode)
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