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參數(shù)資料
| 型號： | MX53L06402L-50 |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | PROM |
| 英文描述： | FLASH 2.7V PROM CARD, XMA7 |
| 封裝： | CRAD-7 |
| 文件頁數(shù)： | 39/55頁 |
| 文件大小： | 262K |
| 代理商： | MX53L06402L-50 |
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44
P/N: PM1043
REV. 1.0, NOV. 25, 2003
MX53L06402
A power-on-reset is generated on chip as long as V
DD is below a certain value. After the power on reset the command
parser of the MX53L06402 works properly, but the access to the memory core is not guaranteed as long as V
DD min
is not reached. Therefore in the power up phase (or when the MX53L06402 is inserted during power up) the host has
to wait after sending the SEND_OP_COND command (CMD1) for the identification delay. After that the ALL_SEND_CID
command(CMD2) can be interpreted by the card:
Figure 22: Power up diagram
For the MX53L06402 the following minimum initialization and identification delays are defined:
Description
Symbol
Minimum Value
Initialization delay
t init
1 ms
@ f clk >64kHz
64 cycles
@ f clk <64kHz
Identification delay
t ident
1 ms
The initialization delay is relevant only after the system power up (>1 ms, at least 64 clock cycles).
The identification delay is relevant for system power up and card hot insertion (> 1 ms). The MX53L06402 ignores
all commands until the sequence CMD1, CMD2 is received and the RCA of the card is ini-tialized. The initialization
delay guarantees enough time for V
DD to reach the minimum operating voltage on the MultiMediaCard bus. The
identification delay guarantees enough time for V
DD to reach the minimum operating voltage internally in the
MultiMediaCard.
Table 28: Initialization and identification delays
VDD max [3.6]
Bus master
supply voltage
VDD min [2.0V]
Power up time
Supply ramp up time
Initlization sequence
Identification delay:
Optional repetitions of CMD1
until no cards are responding
with busy bit set.
The maximum of 1 msec,
74 clock cycles
and supply ramp up time
TIME
NCC
Supply voltage
CMD1
CMD2
CMD1
Card logic working
voltage range
Memory field
working voltage
range
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