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參數(shù)資料
| 型號(hào)： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語(yǔ)音回聲消除器（多通道話音回聲消除器） |
| 文件頁(yè)數(shù)： | 6/37頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | MT9300B |
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MT9300B
Advance Information
6
N1
154
TDO
Test Serial Data Out (Output).
JTAG serial data is output
on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG scan is not enabled.
P1
155
TCK
Test Clock (3.3V Input).
Provides the clock to the JTAG
test logic.
N2
156
TRST
Test Reset (3.3V Input).
Asynchronously initializes the
JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up or held
low, to ensure that the MT9300B is in the normal functional
mode. This pin is pulled by an internal pull-down when not
driven.
R3
158
RESET
Device Reset (Schmitt Trigger Input).
An active low
resets the device and puts the MT9300B into a low-power
stand-by mode.
When the RESET pin is returned to logic high and a
clock is applied to the MCLK pin, the device will
automatically execute initialization routines, which preset
all the Control and Status Registers to their default
power-up values.
C6,D6,J3,J4,N12,P12, G13,G14
V
DD2
These LBGA pins should be wired to V
= 1.8V for
FUTURE USE
. If the customer does not intend to use
future generation of the device, then these pins should
be NO CONNECTS
Pin Description (continued)
Pin #
Name
Description
208-Ball LBGA
160 Pin
MQFP
Device Overview
The
cancellers divided into 16 groups. Each group has
two echo cancellers, Echo Canceller A and Echo
Canceller B. Each group can be configured in
Normal,
Extended
Delay
configurations. In
Normal configuration
, a group of
echo cancellers provides two channels of 64ms echo
cancellation, which run independently on different
channels. In
Extended Delay
configuration, a group
of
echo
cancellers
achieves
cancellation by cascading the two echo cancellers (A
& B). In
Back-to-Back
configuration, the two echo
cancellers from the same group are positioned to
cancel echo coming from both directions in a single
channel,
providing
full-duplex
cancellation.
MT9300B
architecture
contains
32
echo
or
Back-to-Back
128ms
of
echo
64ms
echo
Each echo canceller contains the following main
elements (see Figure 4).
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter
adaptation during periods of double-talk
Path Change detector for fast reconvergence on
major echo path changes
Instability Detector to combat oscillation in very
low ERL environments
Non-Linear Processor for suppression of
residual echo
Disable Tone Detectors for detecting valid
disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive
Filter divergence from narrow-band signals
Offset Null filters for removing the DC
component in PCM channels
12dB attenuator for signal attenuation
Parallel controller interface compatible with
Motorola microcontrollers
PCM encoder/decoder compatible with
μ
/A-Law
ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the MT9300B has four
functional states:
Mute
,
Bypass
,
Disable Adaptation
and
Enable Adaptation
. These are explained in the
section entitled Echo Canceller Functional States.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT9300BL | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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