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參數(shù)資料
| 型號(hào)： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語(yǔ)音回聲消除器（多通道話音回聲消除器） |
| 文件頁(yè)數(shù)： | 5/37頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | MT9300B |
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Advance Information
MT9300B
5
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16, D16
44, 45,46,
47,49, 50,
51,52,54,
55, 56
A0 -
A10
Address A0 to A10 (Input)
. These inputs provide the A10
- A0 address lines to the internal registers.
B13
105
ODE
Output Drive Enable (Input).
This input pin is logically
AND’d with the ODE bit-6 of the Main Control Register.
When both ODE bit and ODE input pin are high, the Rout
and Sout ST-BUS outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the
Rout and Sout ST-BUS outputs are high impedance.
A8
106
Sout
Send PCM Signal Output (Output)
. Port 1 TDM data
output streams.
Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B9
107
Rout
Receive PCM Signal Output (Output)
. Port 2 TDM data
output streams. Rout pin outputs serial TDM data streams
at 2.048 Mb/s with 32 channels per stream.
B11
109
Sin
Send PCM Signal Input (Input).
Port 2 TDM data input
streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B7
110
Rin
Receive PCM Signal Input (Input).
Port 1 TDM data input
streams.
Rin pin receives serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B5
111
F0i
Frame Pulse (Input).
This input accepts and
automatically identifies frame synchronization signals
formatted according to ST-BUS or GCI interface
specifications.
A4
112
C4i
Serial Clock (Input).
4.096 MHz serial clock for shifting
data in/out on the serial streams (Rin, Sin, Rout, Sout).
G2
140
MCLK
Master Clock (Input).
Nominal 10MHz or 20MHz Master
Clock input. May be connected to an asynchronous
(relative to frame signal) clock source.
H2
143
Fsel
Frequency select (Input).
This input selects the Master
Clock frequency operation. When Fsel pin is low, nominal
19.2MHz Master Clock input must be applied. When Fsel
pin is high, nominal 9.6MHz Master Clock input must be
applied.
K3
146
PLLV
SS
PLL Ground.
Must be connected to V
SS
.
PLLV
DD
PLL Power Supply.
Must be connected to V
DD1
.
TMS
Test Mode Select (3.3V Input).
JTAG signal that controls
the state transitions of the TAP controller. This pin is pulled
high by an internal pull-up when not driven.
K4
147
M2
152
M1
153
TDI
Test Serial Data In (3.3V Input).
JTAG serial test
instructions and data are shifted in on this pin. This pin is
pulled high by an internal pull-up when not driven.
Pin Description (continued)
Pin #
Name
Description
208-Ball LBGA
160 Pin
MQFP
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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