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參數資料
| 型號： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數： | 14/37頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MT9300B |
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MT9300B
Advance Information
14
Upon receiving an IRQ, the HOST CPU should read
the Interrupt FIFO Register. This register is a FIFO
memory containing the channel number of the echo
canceller that has generated the interrupt.
All
cancellers
number are stored in this FIFO memory. The IRQ
always returns high after a read access to the
Interrupt FIFO Register. The IRQ pin will toggle low
for each pending interrupt.
pending
interrupts
and
their
from
associated
any
of
input
the
echo
channel
After the HOST CPU has received the channel
number of the interrupt source, the corresponding
per channel Status Register can be read from
internal memory to determine the cause of the
interrupt (see Figure 7 for address mapping of Status
register). The TD bit indicates the presence of a
Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks
interrupts from the MT9300B. To provide more
flexibility, the MTDBI (bit-4) and MTDAI (bit-3) bits in
the Main Control Register<15:0> allow Tone Disable
to be masked or unmasked, from generating an
interrupt on a per channel basis. Refer to the
Registers Description section.
JTAG Support
The MT9300B JTAG interface conforms to the
Boundary-Scan standard IEEE1149.1. This standard
specifies a design-for-testability technique called
Boundary-Scan test (BST). The operation of the
Boundary Scan circuitry is controlled by an external
Test Access Port (TAP) controller. JTAG inputs are
3.3 Volts
compliant only.
Test Access Port (TAP)
The TAP provides access to many test functions of
the MT9300B. It consists of three input pins and one
output pin. The following pins are found on the TAP.
Test Clock Input (TCK)
The TCK provides the clock for the test logic.
The TCK does not interfere with any on-chip
clock and thus remains independent. The TCK
permits shifting of test data into or out of the
Boundary-Scan register cells concurrent with
the operation of the device and without
interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are
interpreted by the TAP Controller to control the
test operations. The TMS signals are sampled
at the rising edge of the TCK pulse. This pin is
internally pulled to V
DD
when it is not driven
from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed
either into the instruction register or into a test
data register, depending on the sequence
previously applied to the TMS input. Both
registers are described in a subsequent
section. The received input data is sampled at
the rising edge of TCK pulses. This pin is
internally pulled to V
DD
when it is not driven from
an external source.
Test Data Output (TDO)
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or data register are serially
shifted out towards the TDO. The data from the
TDO is clocked on the falling edge of the TCK
pulses. When no data is shifted through the
Boundary Scan cells, the TDO driver is set to a
high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan
structure. This pin is internally pulled to V
SS
.
Instruction Register
In accordance with the IEEE 1149.1 standard, the
MT9300B
uses
public
Interface
contains
a
3-bit
Instructions are serially loaded into the instruction
register from the TDI when the TAP Controller is in
its shifted-IR state. Subsequently, the instructions
are decoded to achieve two basic functions: to select
the test data register that will operate while the
instruction is current, and to define the serial test
data register path, which is used to shift data
between TDI and TDO during data register scanning.
instructions.
instruction
The
JTAG
register.
Test Data Registers
As specified in IEEE 1149.1, the MT9300B JTAG
Interface contains three test data registers:
Boundary-Scan register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to form
a scan path around the boundary of the
MT9300B core logic.
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相關代理商/技術參數 |
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|---|---|
| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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