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參數(shù)資料
| 型號： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數(shù)： | 12/37頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MT9300B |
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Advance Information
MT9300B
12
(See Figure 10). In GCI format, every second rising
edge of the C4i clock marks the bit boundary, and
data is clocked in on the second falling edge of C4i,
half the way into the bit cell (see Figure 11).
Figure 8 - Memory Mapping of per channel
Control and Status Registers
Memory Mapped Control and Status
registers
Internal memory and registers are memory mapped
into the address space of the HOST interface. The
internal
dual
ported
memory
segments on a “per channel” basis to monitor and
control
each
individual
associated PCM channels. For example, in
Normal
configuration
, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the
internal address space from 0A0h to 0BFh and
is
mapped
into
echo
canceller
and
interfaces to PCM channel #5 on all serial PCM I/O
streams.
As illustrated in Figure 8, the “per channel” registers
provide independent control and status bits for each
echo canceller. Figure 9 shows the memory map of
the
control/status
register
cancellers.
blocks
for
all
echo
Figure 9 - Memory Mapping
When
configuration is selected, Control Register A1/B1 and
Control Register 2 of the selected group of echo
cancellers require special care. Refer to the Register
description section.
Extended
Delay
or
Back-to-Back
Table 2 is a list of the channels used for the 16
groups of echo cancellers when they are configured
as
Extended Delay
or
Back-to-Back
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O
channels are used. For example, group 1 Echo
Cancellers A and B, channels 2 and 3 are active.
00hControl Reg A1
01h
Decay Step Size Reg
02h
03h
Base
Addr +
Echo Canceller A
04h
06h
Reserved
Flat Delay Reg
Control Reg A2
Status Reg
Reserved
05h
Control Reg A3
08h
Decay Step Number
07h
Reserved
09h
Rin Peak Detect Reg
0Ch
Sin Peak Detect Reg
0Eh
Error Peak Detect Reg
10h
Reserved
12h
DTDT Reg
14h
Reserved
16h
NLPTHR
18h
Step Size, MU
1Ah
Reserved
1Ch
Reserved
1Eh
20hControl Reg B1
21h
Decay Step Size Reg
22h
23h
24h
26h
Reserved
Flat Delay Reg
Control Reg B2
Status Reg
Reserved
25h
Control Reg B3
28h
Decay Step Number
27h
Reserved
29h
Rin Peak Detect Reg
2Ch
Sin Peak Detect Reg
2Eh
Error Peak Detect Reg
30h
Reserved
32h
DTDT Reg
34h
Reserved
36h
NLPTHR
38h
Step Size, MU
3Ah
Reserved
3Ch
Reserved
3Eh
Base
Addr +
Echo Canceller B
Reserved
0Ah
Reserved
0Bh
Reserved
2Ah
Reserved
2Bh
0000H -->
Channel 0, EC A Ctrl/Stat Registers
001FH
0020H -->
Channel 1, EC B Ctrl/Stat Registers
003FH
0040H -->
Channel 2, EC A Ctrl/Stat Registers
005FH
0060H -->
Channel 3, EC B Ctrl/Stat Registers
007FH
03C0H -->
Channel 30, EC A Ctrl/Stat Registers
03DFH
03E0H -->
Channel 31, EC B Ctrl/Stat Registers
03FFH
0400H --> 040FH
Main Control Registers <15:0>
Group 0
Echo
Cancellers
Registers
Groups 2 --> 14
Echo Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Group 15
Echo
Cancellers
Registers
0410H
Interrupt FIFO Register
0411H
Test Register
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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