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參數(shù)資料
| 型號： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數(shù)： | 21/37頁 |
| 文件大小： | 179K |
| 代理商： | MT9300B |
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MT9300B
Advance Information
21
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
15
RP
14
RP
13
RP
12
RP
10
RP
9
RP
8
RP
11
Echo Canceller A, Rin Peak Detect Register 2 (RP)
Echo Canceller B, Rin Peak Detect Register 2 (RP)
Read Address: 0D
H
+ Base Address
Read Address: 2D
H
+ Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
7
RP
6
RP
5
RP
4
RP
2
RP
1
RP
0
RP
3
Echo Canceller A, Rin Peak Detect Register 1 (RP)
Echo Canceller B, Rin Peak Detect Register 1 (RP)
Read Address: 0C
H
+ Base Address
Read Address: 2C
H
+ Base Address
These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
15
SP
14
SP
13
SP
12
SP
10
SP
9
SP
8
SP
11
Echo Canceller A, Sin Peak Detect Register 2 (SP)
Echo Canceller B, Sin Peak Detect Register 2 (SP)
Read Address: 0F
H
+ Base Address
Read Address: 2F
H
+ Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
7
SP
6
SP
5
SP
4
SP
2
SP
1
SP
0
SP
3
Echo Canceller A, Sin Peak Detect Register 1 (SP)
Echo Canceller B, Sin Peak Detect Register 1 (SP)
Read Address: 0E
H
+ Base Address
Read Address: 2E
H
+ Base Address
These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
15
EP
14
EP
13
EP
12
EP
10
EP
9
EP
8
EP
11
Echo Canceller A, Error Peak Detect Register 2 (EP)
Echo Canceller B, Error Peak Detect Register 2 (EP)
Read Address: 11
H
+ Base Address
Read Address: 31
H
+ Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
7
EP
6
EP
5
EP
4
EP
2
EP
1
EP
0
EP
3
Echo Canceller A, Error Peak Detect Register 1 (EP)
Echo Canceller B, Error Peak Detect Register 1 (EP)
Read Address: 10
H
+ Base Address
Read Address: 30
H
+ Base Address
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement
linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in
Register 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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