
MT9300B
Advance Information
10
Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e. DTMF tones)
present in the receive input (Rin) of the echo
canceller for a prolonged period of time may cause
the Adaptive Filter to diverge. The Narrow Band
Signal Detector (NBSD) is designed to prevent this
by detecting single or dual tones of arbitrary
frequency, phase, and amplitude. When narrow band
signals are detected, adaptation is halted but the
echo canceller continues to cancel echo.
The NBSD can be disabled by setting the NBDis bit
to “1” in Control Register 2.
Offset Null Filter
Adaptive filters in general do not operate properly
when a DC offset is present at any inputs. To remove
the DC component, the MT9300B incorporates
Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the
HPFDis bit to “1” in Control Register 2.
ITU-T G.168 Compliance
The MT9300B has been certified G.168 compliant in
all 64 ms cancellation modes (i.e. Normal and Back-
to-Back configurations) by in-house testing with the
DSPG ECT-1 echo canceller tester.
It should be noted that G.168 compliance is not
claimed for the 128 ms Extended Delay mode,
although subjectively no difference can be noticed.
Device Configuration
The
cancellers divided into 16 groups. Each group has
two echo cancellers which can be individually
controlled (Echo Canceller A and B). They can be set
in three distinct configurations:
Normal, Back-to-
Back,
and
Extended Delay
. See Figure 6.
MT9300B
architecture
contains
32
echo
Normal Configuration
In Normal configuration, the two echo cancellers
(Echo Canceller A and B) are positioned in parallel,
as shown in Figure 6a, providing 64 milliseconds of
echo cancellation in two channels simultaneously.
Back-to-Back Configuration
In
Back-to-Back
cancellers from the same group are positioned to
cancel echo coming from both directions in a single
configuration,
the
two
echo
channel
cancellation. See Figure 6c. This configuration uses
only one timeslot on PORT1 and PORT2 and the
second timeslot normally associated with ECB
contains undefined data. Back-to-Back configuration
allows a no-glue interface for applications where
bidirectional echo cancellation is required.
providing
full-duplex
64ms
echo
Back-to-Back configuration is selected by writing “1”
into the BBM bit of
both
Control Register A1 and
Control Register B1 of a given group of echo
cancellers. Table 2 shows the 16 groups of 2
cancellers that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include
positioning one group of echo cancellers between a
CODEC and a transmission device or between two
codecs for echo control on analog trunks.
Extended Delay configuration
In this configuration, the two echo cancellers from
the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 6b. This
configuration uses only one timeslot on PORT1 and
PORT2 and the second timeslot normally associated
with ECB contains undefined data.
Extended Delay configuration is selected by writing
“1” into the ExtDl bit in Echo Canceller A, Control
Register A1. For a given group, only Echo Canceller
A, Control Register A1, has the ExtDl bit. Control
Register B1, bit-0 must always be set to zero.
Table 2 shows the 16 groups of 2 cancellers that can
each be configured into 64ms or 128ms echo tail
capacity.
Echo Canceller Functional States
Each echo canceller has four functional states:
Mute, Bypass, Disable Adaptation
and
Enable
Adaptation
.
Mute
In Normal and in Extended Delay configurations,
writing a “1” into the MuteR bit replaces Rin with
quiet code which is applied to both the Adaptive
Filter and Rout. Writing a “1” into the MuteS bit
replaces the Sout PCM data with quiet code.
LINEAR
16 bits
2’s
complement
SIGN/
-Law
A-Law
MAGNITUDE
CCITT (G.711)
μ
-Law
A-Law
+Zero
(quiet code)
0000h
80h
FFh
D5h
Table 1 - Quiet PCM Code Assignment