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參數(shù)資料
| 型號： | MT9300B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MT9300B |
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Advance Information
MT9300B
11
In Back-to-Back configuration, writing a “1” into the
MuteR bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Rout. Writing
a “1” into the MuteS bit of Echo Canceller A, Control
Register 2, causes quiet code to be transmitted on
Sout.
In
configurations, MuteR and MuteS bits of Echo
Canceller B must always be “0”. Refer to Figure 4
and to Control Register 2 for bit description.
Extended
Delay
and
in
Back -to -Back
Bypass
The Bypass state directly transfers PCM codes from
Rin to Rout and from Sin to Sout.
When Bypass
state is selected, the Adaptive Filter coefficients
are reset to zero.
Bypass state must be selected for
at least one frame (125
μ
s) in order to properly clear
the filter.
Disable Adaptation
When the Disable Adaptation state is selected, the
Adaptive Filter coefficients are frozen at their current
value. The adaptation process is halted, however,
the echo canceller continues to cancel echo.
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter
coefficients are continually updated. This allows
the echo canceller to model the echo return path
characteristics in order to cancel echo. This is the
normal operating state.
The echo canceller functions are selected in Control
Register A1/B1 and Control Register 2 through four
control bits: MuteS, MuteR, Bypass and AdaptDis.
Refer to the Registers Description for details.
MT9300B Throughput Delay
The throughput delay of the MT9300B varies
according to the device configuration. For all device
configurations, Rin to Rout has a delay of two
frames and Sin to Sout has a delay of three frames.
In Bypass state, the Rin to Rout and Sin to Sout
paths have a delay of two frames.
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with
channels numbered from 0 to 31. One set of input
streams is for Receive (Rin) channels, and the other
set of input streams is for Send (Sin) channels.
Likewise, one set of output streams is for Rout pcm
channels, and the other set is for Sout channels. See
Figure 7 for channel allocation.
The arrangement and connection of PCM channels
to each echo canceller is a 2 port I/O configuration
for each set of PCM Send and Receive channels, as
illustrated in Figure 4.
Serial Data Interface Timing
The MT9300B provides ST-BUS and GCI interface
timing. The Serial Interface clock frequency, C4i, is
4.096 MHz. The input and output data rate of the ST-
Bus and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS
or GCI format. The MT9300B automatically detects
the presence of an input frame pulse and identifies it
as either ST-BUS or GCI. In ST-BUS format, every
second falling edge of the C4i clock marks a bit
boundary, and the data is clocked in on the rising
edge of C4i, three quarters of the way into the bit cell
Figure 7 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
F0i
ST-Bus
Rin/Sin
Rout/Sout
Channel 31
Channel 0
125
μ
sec
Channel 1
Channel 30
F0i
GCI interface
Note: Refer to Figures 9 and 10 for timing details
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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